Rainbow-electronics DS26519 Uživatelský manuál

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1 of 310
REV: 040907
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
.
GENERAL DESCRIPTION
The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines. The
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26519
T1/J1/E1
Transceiver
T1/E1/J1
NETWORK
BACKPLANE
TDM
x16
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS26519G
0°C to +70°C
484 HSBGA
DS26519G+
0°C to +70°C
484 HSBGA
DS26519GN
-40°C to +85°C
484 HSBGA
DS26519GN+
-40°C to +85°C
484 HSBGA
+ Denotes lead-free/RoHS compliant device.
FEATURES
16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75Ω E1 Coaxial Applications
Hitless Protection Switching
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section 2
.
DS26519
16-Port T1/E1/J1 Transceive
r
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Strany 1 - 16-Port T1/E1/J1 Transceive

1 of 310 REV: 040907 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revision

Strany 2 - TABLE OF CONTENTS

DS26519 16-Port T1/E1/J1 Transceiver 10 of 310 2. FEATURE HIGHLIGHTS 2.1 General  23mm x 23mm, 484-pin HSBGA (1.00mm pitch)  3.3V and 1.8V supply

Strany 3

DS26519 16-Port T1/E1/J1 Transceiver 100 of 310 Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications STANDARD CRITERIA T1.231 ITU

Strany 4

DS26519 16-Port T1/E1/J1 Transceiver 101 of 310 9.12.4 Hitless Protection Switching (HPS) Many current redundancy protection implementations use mec

Strany 5 - LIST OF FIGURES

DS26519 16-Port T1/E1/J1 Transceiver 102 of 310 9.12.5 Jitter Attenuator The DS26519 contains a jitter attenuator that can be set to a depth of 32 or

Strany 6

DS26519 16-Port T1/E1/J1 Transceiver 103 of 310 9.12.6 LIU Loopbacks The DS26519 provides four LIU loopbacks for diagnostic purposes: Analog Loopback

Strany 7 - LIST OF TABLES

DS26519 16-Port T1/E1/J1 Transceiver 104 of 310 9.12.6.2 Local Loopback The transmit system data is looped back to the receive framer. This data is a

Strany 8

DS26519 16-Port T1/E1/J1 Transceiver 105 of 310 9.12.6.5 Dual Loopback The inputs decoded from the receive LIU are looped back to the transmit LIU. T

Strany 9 - 1. DETAILED DESCRIPTION

DS26519 16-Port T1/E1/J1 Transceiver 106 of 310 9.13 Bit Error-Rate Test Function (BERT) The BERT (Bit Error Rate Tester) block can generate and det

Strany 10 - 2. FEATURE HIGHLIGHTS

DS26519 16-Port T1/E1/J1 Transceiver 107 of 310 The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E

Strany 11 - 2.6 System Interface

DS26519 16-Port T1/E1/J1 Transceiver 108 of 310 10. DEVICE REGISTERS Fourteen address bits are used to control the settings of the registers. The reg

Strany 12 - 2.8 Test and Diagnostics

DS26519 16-Port T1/E1/J1 Transceiver 109 of 310 10.1.1 Global Register List Table 10-2. Global Register Mapping CHANNEL REGISTER ADDRESS (HEX) 1–8 0

Strany 13 - 3. APPLICATIONS

DS26519 16-Port T1/E1/J1 Transceiver 11 of 310 2.5 Framer/Formatter  Fully independent transmit and receive functionality  Full receive and trans

Strany 14 - 4. SPECIFICATIONS COMPLIANCE

DS26519 16-Port T1/E1/J1 Transceiver 110 of 310 10.1.2 Framer Register List Table 10-4. Framer Register List Note that only Framer 1 address is pres

Strany 15

DS26519 16-Port T1/E1/J1 Transceiver 111 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W RIDR30 Receive Idle Code Definition Register 30

Strany 16 - 5. ACRONYMS AND GLOSSARY

DS26519 16-Port T1/E1/J1 Transceiver 112 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 080h RMMR Receive Master Mode Register R/W RCR1

Strany 17 - 6. MAJOR OPERATING MODES

DS26519 16-Port T1/E1/J1 Transceiver 113 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 0B1h — Reserved — RRTS3 Receive Real-Time Status

Strany 18 - 7. BLOCK DIAGRAMS

DS26519 16-Port T1/E1/J1 Transceiver 114 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 118h SSIE1 Software-Signaling Insertion Enable R

Strany 19 - 19 of 310

DS26519 16-Port T1/E1/J1 Transceiver 115 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 150h TCICE1 Transmit Channel Idle Code Enable Re

Strany 20 - 8. PIN DESCRIPTIONS

DS26519 16-Port T1/E1/J1 Transceiver 116 of 310 FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 1B4h THF Transmit HDLC FIFO Register W 1B5h–1Bh

Strany 21 - 21 of 310

DS26519 16-Port T1/E1/J1 Transceiver 117 of 310 10.1.3 LIU and BERT Register List Table 10-5. LIU Register List Note that only the LIU 1 address is

Strany 22 - 22 of 310

DS26519 16-Port T1/E1/J1 Transceiver 118 of 310 10.2 Register Bit Maps 10.2.1 Global Register Bit Map Table 10-7. Global Register Bit Map ADDR (1–8)

Strany 23 - 23 of 310

DS26519 16-Port T1/E1/J1 Transceiver 119 of 310 10.2.2 Framer Register Bit Map Table 10-8 contains the framer registers of the DS26519. Some registe

Strany 24 - 24 of 310

DS26519 16-Port T1/E1/J1 Transceiver 12 of 310  Signaling freezing  Ability to pass the T1 F-bit position through the elastic stores in the 2.04

Strany 25 - 25 of 310

DS26519 16-Port T1/E1/J1 Transceiver 120 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T1RSAOI3 CH24 CH23 CH22 CH21 C

Strany 26 - 26 of 310

DS26519 16-Port T1/E1/J1 Transceiver 121 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 054h FOSCR1 FOS15 FOS14 FOS13 FOS

Strany 27 - 27 of 310

DS26519 16-Port T1/E1/J1 Transceiver 122 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RLS3 (E1) LORCC — V52LNKC RDMAC

Strany 28 - 28 of 310

DS26519 16-Port T1/E1/J1 Transceiver 123 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0C5h RCBR2 CH16 CH15 CH14 CH13 CH

Strany 29 - 29 of 310

DS26519 16-Port T1/E1/J1 Transceiver 124 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 126h TIDR7 C7 C6 C5 C4 C3 C2 C1 C0

Strany 30 - 30 of 310

DS26519 16-Port T1/E1/J1 Transceiver 125 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CH7-A CH7-B CH7-C CH7-D CH22

Strany 31 - 31 of 310

DS26519 16-Port T1/E1/J1 Transceiver 126 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T1.TCR2 (T1) TFDLS TSLC96 TDDSEN

Strany 32 - 32 of 310

DS26519 16-Port T1/E1/J1 Transceiver 127 of 310 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1CAh THSCS3 CH24 CH23 CH22 CH21 C

Strany 33 - 9. FUNCTIONAL DESCRIPTION

DS26519 16-Port T1/E1/J1 Transceiver 128 of 310 10.2.3 LIU Register Bit Map Table 10-9. LIU Register Bit Map ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4

Strany 34

DS26519 16-Port T1/E1/J1 Transceiver 129 of 310 10.2.4 BERT Register Bit Map Table 10-10. BERT Register Bit Map ADDR NAME BIT 7 BIT 6 BIT 5 BIT

Strany 35

DS26519 16-Port T1/E1/J1 Transceiver 13 of 310 3. APPLICATIONS The DS26519 is useful in applications such as:  Routers  Channel Service Units (CS

Strany 36

DS26519 16-Port T1/E1/J1 Transceiver 130 of 310 10.3 Global Register Definitions Functions contained in the global registers include: framer reset,

Strany 37

DS26519 16-Port T1/E1/J1 Transceiver 131 of 310 Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 00

Strany 38 - Table 9-2. Reset Functions

DS26519 16-Port T1/E1/J1 Transceiver 132 of 310 Register Name GTCR2 Register Description: Global Transceiver Control Register 2 Register Address: 20

Strany 39

DS26519 16-Port T1/E1/J1 Transceiver 133 of 310 Register Name: GFCR1 Description: Global Framer Control Register 1 Register Address: 00F1h Channels:

Strany 40

DS26519 16-Port T1/E1/J1 Transceiver 134 of 310 Register Name: GFCR2 Description: Global Framer Control Register 2 Register Address: 20F1h Channels:

Strany 41 - 9.7 Device Interrupts

DS26519 16-Port T1/E1/J1 Transceiver 135 of 310 Register Name: GTCR3 Register Description: Global Transceiver Control Register 3 Register Address:

Strany 42

DS26519 16-Port T1/E1/J1 Transceiver 136 of 310 Register Name: GTCCR1 Register Description: Global Transceiver Clock Control Register 1 Register Add

Strany 43 - 9.8.1 Elastic Stores

DS26519 16-Port T1/E1/J1 Transceiver 137 of 310 Table 10-15. Backplane Reference Clock Select (1 to 8) BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQS

Strany 44

DS26519 16-Port T1/E1/J1 Transceiver 138 of 310 Register Name: GTCCR2 Register Description: Global Transceiver Clock Control Register 2 Register Add

Strany 45

DS26519 16-Port T1/E1/J1 Transceiver 139 of 310 Register Name: GTCCR3 Register Description: Global Transceiver Clock Control Register 3 Register Addr

Strany 46 - 9.8.2 IBO Multiplexing

DS26519 16-Port T1/E1/J1 Transceiver 14 of 310 4. SPECIFICATIONS COMPLIANCE The DS26519 meets all the latest relevant telecommunications specificatio

Strany 47

DS26519 16-Port T1/E1/J1 Transceiver 140 of 310 Register Name: GTCCR4 Register Description: Global Transceiver Clock Control Register 4 Register Add

Strany 48

DS26519 16-Port T1/E1/J1 Transceiver 141 of 310 Register Name: GSRR1 Register Description: Global LIU Software Reset Register 1 Register Address: 00

Strany 49

DS26519 16-Port T1/E1/J1 Transceiver 142 of 310 Register Name: IDR Register Description: Device Identification Register Register Address: 00F8h Bit

Strany 50

DS26519 16-Port T1/E1/J1 Transceiver 143 of 310 Register Name: GFISR1 Register Description: Global Framer Interrupt Status Register 1 Register Addre

Strany 51

DS26519 16-Port T1/E1/J1 Transceiver 144 of 310 Register Name: GFISR2 Register Description: Global Framer Interrupt Status Register 2 Register Addre

Strany 52

DS26519 16-Port T1/E1/J1 Transceiver 145 of 310 Register Name: GBISR1 Register Description: Global BERT Interrupt Status Register 1 Register Address

Strany 53

DS26519 16-Port T1/E1/J1 Transceiver 146 of 310 Register Name: GBISR2 Register Description: Global BERT Interrupt Status Register 2 Register Address

Strany 54

DS26519 16-Port T1/E1/J1 Transceiver 147 of 310 Register Name: GLISR1 Register Description: Global LIU Interrupt Status Register 1 Register Address:

Strany 55

DS26519 16-Port T1/E1/J1 Transceiver 148 of 310 Register Name: GLISR2 Register Description: Global LIU Interrupt Status Register 2 Register Address:

Strany 56

DS26519 16-Port T1/E1/J1 Transceiver 149 of 310 Register Name: GFIMR1 Register Description: Global Framer Interrupt Mask Register 1 Register Address

Strany 57

DS26519 16-Port T1/E1/J1 Transceiver 15 of 310 Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristic

Strany 58 - Table 9-11. D4 Framing Mode

DS26519 16-Port T1/E1/J1 Transceiver 150 of 310 Register Name: GFIMR2 Register Description: Global Framer Interrupt Mask Register 2 Register Address

Strany 59 - Table 9-13. SLC-96 Framing

DS26519 16-Port T1/E1/J1 Transceiver 151 of 310 Register Name: GBIMR1 Register Description: Global BERT Interrupt Mask Register 1 Register Address:

Strany 60 - 60 of 310

DS26519 16-Port T1/E1/J1 Transceiver 152 of 310 Register Name: GBIMR2 Register Description: Global BERT Interrupt Mask Register 2 Register Address:

Strany 61 - 9.9.2 E1 Framing

DS26519 16-Port T1/E1/J1 Transceiver 153 of 310 Register Name: GLIMR1 Register Description: Global LIU Interrupt Mask Register 1 Register Address: 0

Strany 62

DS26519 16-Port T1/E1/J1 Transceiver 154 of 310 Register Name: GLIMR2 Register Description: Global LIU Interrupt Mask Register 2 Register Address: 2

Strany 63

DS26519 16-Port T1/E1/J1 Transceiver 155 of 310 Register Name: GPIORR1 Register Description: General-Purpose I/O Read Register 1 Register Address: 0

Strany 64 - 9.9.4 Signaling

DS26519 16-Port T1/E1/J1 Transceiver 156 of 310 10.4 Framer Register Descriptions 10.4.1 Receive Register Descriptions See Table 10-4 for the compl

Strany 65

DS26519 16-Port T1/E1/J1 Transceiver 157 of 310 Register Name: RHBSE Register Description: Receive HDLC Bit Suppress Register Register Address: 011h

Strany 66 - 9.9.4.2.2 Change of State

DS26519 16-Port T1/E1/J1 Transceiver 158 of 310 Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Register Addres

Strany 67

DS26519 16-Port T1/E1/J1 Transceiver 159 of 310 Register Name: T1RCR2 (T1 Mode) Register Description: Receive Control Register 2 Register Address: 0

Strany 68

DS26519 16-Port T1/E1/J1 Transceiver 16 of 310 5. ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating

Strany 69 - 9.9.5 T1 Data Link

DS26519 16-Port T1/E1/J1 Transceiver 160 of 310 Register Name: E1RSAIMR (E1 Mode Only) Register Description: Receive Sa Bit Interrupt Mask Register

Strany 70

DS26519 16-Port T1/E1/J1 Transceiver 161 of 310 Register Name: T1RBOCC (T1 Mode Only) Register Description: Receive BOC Control Register Register Ad

Strany 71 - 9.9.6 E1 Data Link

DS26519 16-Port T1/E1/J1 Transceiver 162 of 310 Register Name: T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Register Description: Receive-Signaling A

Strany 72

DS26519 16-Port T1/E1/J1 Transceiver 163 of 310 Register Name: RS1 to RS16 Register Description: Receive-Signaling Registers 1 to 16 Register Addres

Strany 73

DS26519 16-Port T1/E1/J1 Transceiver 164 of 310 Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 0

Strany 74 - 9.9.7.1.3 Mask Bits

DS26519 16-Port T1/E1/J1 Transceiver 165 of 310 Register Name: FOSCR1 Register Description: Frames Out of Sync Count Register 1 Register Address: 05

Strany 75 - 9.9.8 Alarms

DS26519 16-Port T1/E1/J1 Transceiver 166 of 310 Register Name: FEACR1 Register Description: Error Count A Register 1 Register Address: 058h + (200h

Strany 76

DS26519 16-Port T1/E1/J1 Transceiver 167 of 310 Register Name: RDS0M Register Description: Receive DS0 Monitor Register Register Address: 060h + (20

Strany 77 - 9.9.9 Error Count Registers

DS26519 16-Port T1/E1/J1 Transceiver 168 of 310 Register Name: T1RFDL (T1 Mode) Register Description: Receive FDL Register Register Address: 062h +

Strany 78

DS26519 16-Port T1/E1/J1 Transceiver 169 of 310 Register Name: T1RBOC (T1 Mode) Register Description: Receive BOC Register Register Address: 63h + (

Strany 79

DS26519 16-Port T1/E1/J1 Transceiver 17 of 310 6. MAJOR OPERATING MODES The DS26519 has two major modes of operation: T1 mode and E1 mode. The mode

Strany 80 - 9.9.13 Per-Channel Loopback

DS26519 16-Port T1/E1/J1 Transceiver 170 of 310 Register Name: T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Register Description: Receive SLC96 Data Link Reg

Strany 81

DS26519 16-Port T1/E1/J1 Transceiver 171 of 310 Register Name: E1RNAF (E1 Mode) Register Description: E1 Receive Non-Align Frame Register Register A

Strany 82

DS26519 16-Port T1/E1/J1 Transceiver 172 of 310 Register Name: E1RSiNAF (E1 Mode Only) Register Description: Receive Si Bits of the Non-Align Frame

Strany 83

DS26519 16-Port T1/E1/J1 Transceiver 173 of 310 Register Name: E1RSa4 (E1 Mode Only) Register Description: Received Sa4 Bits Register Register Addre

Strany 84 - 9.10 HDLC Controllers

DS26519 16-Port T1/E1/J1 Transceiver 174 of 310 Register Name: E1RSa6 (E1 Mode Only) Register Description: Received Sa6 Bits Register Register Addre

Strany 85

DS26519 16-Port T1/E1/J1 Transceiver 175 of 310 Register Name: E1RSa8 (E1 Mode Only) Register Description: Received Sa8 Bits Register Register Addre

Strany 86 - 86 of 310

DS26519 16-Port T1/E1/J1 Transceiver 176 of 310 Register Name: Sa6CODE Register Description: Received Sa6 Codeword Register Register Address: 06Fh +

Strany 87

DS26519 16-Port T1/E1/J1 Transceiver 177 of 310 Register Name: RCR1 (T1 Mode) Register Description: Receive Control Register 1 Register Address: 081

Strany 88 - 88 of 310

DS26519 16-Port T1/E1/J1 Transceiver 178 of 310 Register Name: RCR1 (E1 Mode) Register Description: Receive Control Register 1 Register Address: 081

Strany 89 - 9.11 Power-Supply Decoupling

DS26519 16-Port T1/E1/J1 Transceiver 179 of 310 Register Name: T1RIBCC (T1 Mode) Register Description: Receive In-Band Code Control Register Registe

Strany 90

DS26519 16-Port T1/E1/J1 Transceiver 18 of 310 7. BLOCK DIAGRAMS Figure 7-1. Block Diagram x16DS26519FRAMER #16FRAMER #15FRAMER #14...FRAMER #4FRAMER

Strany 91

DS26519 16-Port T1/E1/J1 Transceiver 180 of 310 Register Name: RCR3 Register Description: Receive Control Register 3 Register Address: 083h + (200h

Strany 92 - 9.12.1 LIU Operation

DS26519 16-Port T1/E1/J1 Transceiver 181 of 310 Register Name: E1RDMWE1, E1RDMWE2, E1RDMWE3, E1RDMWE4 Register Description: E1 Receive Digital Milli

Strany 93 - 9.12.2 Transmitter

DS26519 16-Port T1/E1/J1 Transceiver 182 of 310 Register Name: RIOCR Register Description: Receive I/O Configuration Register Register Address: 084h

Strany 94 - I.431 Template

DS26519 16-Port T1/E1/J1 Transceiver 183 of 310 Register Name: RESCR Register Description: Receive Elastic Store Control Register Register Address:

Strany 95 - 95 of 310

DS26519 16-Port T1/E1/J1 Transceiver 184 of 310 Register Name: ERCNT Register Description: Error Counter Configuration Register Register Address: 086

Strany 96

DS26519 16-Port T1/E1/J1 Transceiver 185 of 310 Register Name: RHFC Register Description: Receive HDLC FIFO Control Register Register Address: 087h

Strany 97 - 9.12.3 Receiver

DS26519 16-Port T1/E1/J1 Transceiver 186 of 310 Register Name: T1RSCC (T1 Mode Only) Register Description: In-Band Receive Spare Control Register Re

Strany 98

DS26519 16-Port T1/E1/J1 Transceiver 187 of 310 Register Name: RBPBS Register Description: Receive BERT Port Bit Suppress Register Register Address:

Strany 99

DS26519 16-Port T1/E1/J1 Transceiver 188 of 310 Register Name: RLS1 Register Description: Receive Latched Status Register 1 Register Address: 090h +

Strany 100

DS26519 16-Port T1/E1/J1 Transceiver 189 of 310 Register Name: RLS2 (T1 Mode) Register Description: Receive Latched Status Register 2 Register Addre

Strany 101 - CONTROL

DS26519 16-Port T1/E1/J1 Transceiver 19 of 310 Figure 7-2. Detailed Block Diagram CLOCKSYNTHESIZ-ERMICROPROCESSORINTERFACEJTAGPORTRESETBLOCKA[13:0]D[

Strany 102 - 9.12.5 Jitter Attenuator

DS26519 16-Port T1/E1/J1 Transceiver 190 of 310 Register Name: RLS3 (T1 Mode) Register Description: Receive Latched Status Register 3 Register Addre

Strany 103 - Figure 9-28. Analog Loopback

DS26519 16-Port T1/E1/J1 Transceiver 191 of 310 Register Name: RLS3 (E1 Mode) Register Description: Receive Latched Status Register 3 Register Addre

Strany 104 - Receive

DS26519 16-Port T1/E1/J1 Transceiver 192 of 310 Register Name: RLS4 Register Description: Receive Latched Status Register 4 Register Address: 093h +

Strany 105 - Figure 9-31. Dual Loopback

DS26519 16-Port T1/E1/J1 Transceiver 193 of 310 Register Name: RLS5 Register Description: Receive Latched Status Register 5 (HDLC) Register Address:

Strany 106

DS26519 16-Port T1/E1/J1 Transceiver 194 of 310 Register Name: RLS7 (T1 Mode) Register Description: Receive Latched Status Register 7 Register Addr

Strany 107 - 9.13.2 BERT Error Counter

DS26519 16-Port T1/E1/J1 Transceiver 195 of 310 Register Name: RSS1, RSS2, RSS3, RSS4 Register Description: Receive-Signaling Status Registers 1 to

Strany 108 - 10. DEVICE REGISTERS

DS26519 16-Port T1/E1/J1 Transceiver 196 of 310 Register Name: T1RSCD1 (T1 Mode Only) Register Description: Receive Spare Code Definition Register 1

Strany 109 - 10.1.1 Global Register List

DS26519 16-Port T1/E1/J1 Transceiver 197 of 310 Register Name: RIIR Register Description: Receive Interrupt Information Register Register Address: 9

Strany 110 - 10.1.2 Framer Register List

DS26519 16-Port T1/E1/J1 Transceiver 198 of 310 Register Name: RIM2 (E1 Mode Only) Register Description: E1 Receive Interrupt Mask Register 2 Regist

Strany 111

DS26519 16-Port T1/E1/J1 Transceiver 199 of 310 Register Name: RIM3 (T1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Addre

Strany 112

DS26519 16-Port T1/E1/J1 Transceiver 2 of 310 TABLE OF CONTENTS 1. DETAILED DESCRIPTION...

Strany 113

DS26519 16-Port T1/E1/J1 Transceiver 20 of 310 8. PIN DESCRIPTIONS 8.1 Pin Functional Description Table 8-1. Detailed Pin Descriptions NAME PIN TYPE

Strany 114

DS26519 16-Port T1/E1/J1 Transceiver 200 of 310 Register Name: RIM3 (E1 Mode) Register Description: E1 Receive Interrupt Mask Register 3 Register Ad

Strany 115

DS26519 16-Port T1/E1/J1 Transceiver 201 of 310 Register Name: RIM4 Register Description: Receive Interrupt Mask Register 4 Register Address: 0A3h +

Strany 116

DS26519 16-Port T1/E1/J1 Transceiver 202 of 310 Register Name: RIM5 Register Description: Receive Interrupt Mask 5 (HDLC) Register Address: 0A4h + (

Strany 117

DS26519 16-Port T1/E1/J1 Transceiver 203 of 310 Register Name: RIM7 (T1 Mode) Register Description: Receive Interrupt Mask Register 7 (BOC:FDL) Regi

Strany 118 - TSSYNCIOSEL

DS26519 16-Port T1/E1/J1 Transceiver 204 of 310 Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive-Signaling Change of Stat

Strany 119

DS26519 16-Port T1/E1/J1 Transceiver 205 of 310 Register Name: T1RUPCD1 (T1 Mode Only) Register Description: Receive Up Code Definition Register 1 R

Strany 120 - — — — — — —

DS26519 16-Port T1/E1/J1 Transceiver 206 of 310 Register Name: T1RDNCD1 (T1 Mode Only) Register Description: Receive Down Code Definition Register 1

Strany 121 - 121 of 310

DS26519 16-Port T1/E1/J1 Transceiver 207 of 310 Register Name: RRTS1 Register Description: Receive Real-Time Status Register 1 Register Address: 0B0

Strany 122 - — — — — — — — —

DS26519 16-Port T1/E1/J1 Transceiver 208 of 310 Register Name: RRTS3 (T1 Mode) Register Description: Receive Real-Time Status Register 3 Register Ad

Strany 123 - 123 of 310

DS26519 16-Port T1/E1/J1 Transceiver 209 of 310 Register Name: RRTS5 Register Description: Receive Real-Time Status Register 5 (HDLC) Register Addre

Strany 124 - 124 of 310

DS26519 16-Port T1/E1/J1 Transceiver 21 of 310 NAME PIN TYPE FUNCTION ANALOG RECEIVE RTIP1 B4 RTIP2 T2 RTIP3 U1 RTIP4 Y2 RTIP5 AA20 RTIP6 J21 RTIP7

Strany 125 - 125 of 310

DS26519 16-Port T1/E1/J1 Transceiver 210 of 310 Register Name: RHF Register Description: Receive HDLC FIFO Register Register Address: 0B6h + (200h x

Strany 126 - 126 of 310

DS26519 16-Port T1/E1/J1 Transceiver 211 of 310 Register Name: RCBR1, RCBR2, RCBR3, RCBR4 Register Description: Receive Channel Blocking Registers 1

Strany 127 - 127 of 310

DS26519 16-Port T1/E1/J1 Transceiver 212 of 310 Register Name: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Register Description: Receive Gapped Clock Channel Sel

Strany 128 - 10.2.3 LIU Register Bit Map

DS26519 16-Port T1/E1/J1 Transceiver 213 of 310 Register Name: RBPCS1, RBPCS2, RBPCS3, RBPCS4 Register Description: Receive BERT Port Channel Select

Strany 129

DS26519 16-Port T1/E1/J1 Transceiver 214 of 310 10.4.2 Transmit Register Descriptions Register Name: THC1 Register Description: Transmit HDLC Contr

Strany 130

DS26519 16-Port T1/E1/J1 Transceiver 215 of 310 Register Name: THBSE Register Description: Transmit HDLC Bit Suppress Register Address: 111h + (200h

Strany 131 - Channels:

DS26519 16-Port T1/E1/J1 Transceiver 216 of 310 Register Name: E1TSACR Register Description: E1 Transmit Sa-Bit Control Register Register Address: 1

Strany 132

DS26519 16-Port T1/E1/J1 Transceiver 217 of 310 Register Name: SSIE1, SSIE2, SSIE3, SSIE4 Register Description: Software-Signaling Insertion Enable

Strany 133 - Description:

DS26519 16-Port T1/E1/J1 Transceiver 218 of 310 Register Name: TS1 to TS16 Register Description: Transmit-Signaling Registers Register Address: 140h

Strany 134

DS26519 16-Port T1/E1/J1 Transceiver 219 of 310 Register Name: TCICE1, TCICE2, TCICE3, TCICE4 Register Description: Transmit Channel Idle Code Enabl

Strany 135

DS26519 16-Port T1/E1/J1 Transceiver 22 of 310 NAME PIN TYPE FUNCTION TRANSMIT FRAMER TSER1 B15 TSER2 D14 TSER3 T8 TSER4 R12 TSER5 T10 TSER6 U11 TSE

Strany 136

DS26519 16-Port T1/E1/J1 Transceiver 220 of 310 Register Name: TDDS1, TDDS2, TDDS3 Register Description: Transmit DDS Zero Code Registers 1 to 3 Reg

Strany 137

DS26519 16-Port T1/E1/J1 Transceiver 221 of 310 Register Name: T1TBOC Register Description: Transmit BOC Register Register Address: 163h + (200h x (

Strany 138

DS26519 16-Port T1/E1/J1 Transceiver 222 of 310 Register Name: T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Register Description: Transmit SLC-96 Data Link R

Strany 139 - — RSYSCLKSEL TSYSCLKSEL

DS26519 16-Port T1/E1/J1 Transceiver 223 of 310 Register Name: E1TSiAF (E1 Mode) Register Description: Transmit Si Bits of the Align Frame Register

Strany 140

DS26519 16-Port T1/E1/J1 Transceiver 224 of 310 Register Name: E1TRA (E1 Mode Only) Register Description: Transmit Remote Alarm Register Register Ad

Strany 141

DS26519 16-Port T1/E1/J1 Transceiver 225 of 310 Register Name: E1TSa5 (E1 Mode Only) Register Description: Transmit Sa5 Bits Register Register Addre

Strany 142

DS26519 16-Port T1/E1/J1 Transceiver 226 of 310 Register Name: E1TSa7 (E1 Mode Only) Register Description: Transmit Sa7 Bits Register Register Addre

Strany 143

DS26519 16-Port T1/E1/J1 Transceiver 227 of 310 Register Name: TMMR Register Description: Transmit Master Mode Register Register Address: 180h + (2

Strany 144

DS26519 16-Port T1/E1/J1 Transceiver 228 of 310 Register Name: TCR1 (T1 Mode) Register Description: Transmit Control Register 1 Register Address: 18

Strany 145

DS26519 16-Port T1/E1/J1 Transceiver 229 of 310 Register Name: TCR1 (E1 Mode) Register Description: Transmit Control Register 1 Register Address: 1

Strany 146

DS26519 16-Port T1/E1/J1 Transceiver 23 of 310 NAME PIN TYPE FUNCTION TSYNC1/ TSSYNCIO1 F8 TSYNC2/ TSSYNCIO2 D13 TSYNC3/ TSSYNCIO3 R9 TSYNC4/ TSSYNC

Strany 147

DS26519 16-Port T1/E1/J1 Transceiver 230 of 310 Register Name: T1.TCR2 (T1 Mode) Register Description: Transmit Control Register 2 Register Address:

Strany 148

DS26519 16-Port T1/E1/J1 Transceiver 231 of 310 Register Name: E1.TCR2 (E1 Mode) Register Description: Transmit Control Register 2 Register Address:

Strany 149

DS26519 16-Port T1/E1/J1 Transceiver 232 of 310 Register Name: TCR3 Register Description: Transmit Control Register 3 Register Address: 183h + (200h

Strany 150

DS26519 16-Port T1/E1/J1 Transceiver 233 of 310 Register Name: TIOCR Register Description: Transmit I/O Configuration Register Register Address: 18

Strany 151

DS26519 16-Port T1/E1/J1 Transceiver 234 of 310 Register Name: TESCR Register Description: Transmit Elastic Store Control Register Register Address

Strany 152

DS26519 16-Port T1/E1/J1 Transceiver 235 of 310 Register Name: TCR4 Register Description: Transmit Control Register 4 Register Address: 186h + (200

Strany 153

DS26519 16-Port T1/E1/J1 Transceiver 236 of 310 Register Name: THFC Register Description: Transmit HDLC FIFO Control Register Register Address: 187h

Strany 154

DS26519 16-Port T1/E1/J1 Transceiver 237 of 310 Register Name: TXPC Register Description: Transmit Expansion Port Control Register Register Address:

Strany 155

DS26519 16-Port T1/E1/J1 Transceiver 238 of 310 Register Name: TBPBS Register Description: Transmit BERT Port Bit Suppress Register Register Address

Strany 156

DS26519 16-Port T1/E1/J1 Transceiver 239 of 310 Register Name: TLS1 Register Description: Transmit Latched Status Register 1 Register Address: 190h

Strany 157

DS26519 16-Port T1/E1/J1 Transceiver 24 of 310 NAME PIN TYPE FUNCTION TCHBLK1/ TCHCLK1 A15 TCHBLK2/ TCHCLK2 A17 TCHBLK3/ TCHCLK3 N9 TCHBLK4/ TCHCLK4

Strany 158

DS26519 16-Port T1/E1/J1 Transceiver 240 of 310 Register Name: TLS2 Register Description: Transmit Latched Status Register 2 (HDLC) Register Address

Strany 159

DS26519 16-Port T1/E1/J1 Transceiver 241 of 310 Register Name: TIIR Register Description: Transmit Interrupt Information Register Register Address:

Strany 160

DS26519 16-Port T1/E1/J1 Transceiver 242 of 310 Register Name: TIM1 Register Description: Transmit Interrupt Mask Register 1 Register Address: 1A0h

Strany 161

DS26519 16-Port T1/E1/J1 Transceiver 243 of 310 Register Name: TIM2 Register Description: Transmit Interrupt Mask Register 2 Register Address: 1A1h

Strany 162

DS26519 16-Port T1/E1/J1 Transceiver 244 of 310 Register Name: T1TCD1 (T1 Mode Only) Register Description: Transmit Code Definition Register 1 Regis

Strany 163

DS26519 16-Port T1/E1/J1 Transceiver 245 of 310 Register Name: TRTS2 Register Description: Transmit Real-Time Status Register 2 (HDLC) Register Addr

Strany 164

DS26519 16-Port T1/E1/J1 Transceiver 246 of 310 Register Name: TDS0M Register Description: Transmit DS0 Monitor Register Register Address: 1BBh + (2

Strany 165

DS26519 16-Port T1/E1/J1 Transceiver 247 of 310 Register Name: TCBR1, TCBR2, TCBR3, TCBR4 Register Description: Transmit Channel Blocking Registers

Strany 166

DS26519 16-Port T1/E1/J1 Transceiver 248 of 310 Register Name: TGCCS1, TGCCS2, TGCCS3, TGCCS4 Register Description: Transmit Gapped Clock Channel Se

Strany 167

DS26519 16-Port T1/E1/J1 Transceiver 249 of 310 Register Name: TBPCS1, TBPCS2, TBPCS3, TBPCS4 Register Description: Transmit BERT Port Channel Selec

Strany 168

DS26519 16-Port T1/E1/J1 Transceiver 25 of 310 NAME PIN TYPE FUNCTION RECEIVE FRAMER RSER1 D12 RSER2 E12 RSER3 J5 RSER4 AA4 RSER5 Y10 RSER6 AA10 RSE

Strany 169

DS26519 16-Port T1/E1/J1 Transceiver 250 of 310 10.5 LIU Register Definitions Table 10-18. LIU Register Set ADDRESS NAME DESCRIPTION R/W 1000h LT

Strany 170

DS26519 16-Port T1/E1/J1 Transceiver 251 of 310 Register Name: LTRCR Register Description: LIU Transmit Receive Control Register Register Addresses:

Strany 171

DS26519 16-Port T1/E1/J1 Transceiver 252 of 310 Register Name: LTIPSR Register Description: LIU Transmit Impedance and Pulse Shape Selection Registe

Strany 172

DS26519 16-Port T1/E1/J1 Transceiver 253 of 310 Register Name: LMCR Register Description: LIU Maintenance Control Register Register Address: 1002h +

Strany 173

DS26519 16-Port T1/E1/J1 Transceiver 254 of 310 Register Name: LRSR Register Description: LIU Real Status Register Register Address: 1003h + (20h x

Strany 174

DS26519 16-Port T1/E1/J1 Transceiver 255 of 310 Register Name: LSIMR Register Description: LIU Status Interrupt Mask Register Register Address: 1004

Strany 175

DS26519 16-Port T1/E1/J1 Transceiver 256 of 310 Register Name: LLSR Register Description: LIU Latched Status Register Register Address: 1005h + (20h

Strany 176

DS26519 16-Port T1/E1/J1 Transceiver 257 of 310 Register Name: LRSL Register Description: LIU Receive Signal Level Register Register Address: 1006h

Strany 177

DS26519 16-Port T1/E1/J1 Transceiver 258 of 310 Register Name: LRISMR Register Description: LIU Receive Impedance and Sensitivity Monitor Register

Strany 178

DS26519 16-Port T1/E1/J1 Transceiver 259 of 310 Register Name: LRCR Register Description: LIU Receive Control Register Register Address: 1008h + (20

Strany 179

DS26519 16-Port T1/E1/J1 Transceiver 26 of 310 NAME PIN TYPE FUNCTION RSYNC1 F9 RSYNC2 E13 RSYNC2 T7 RSYNC2 W3 RSYNC5 W9 RSYNC6 AB9 RSYNC7 A19 RSYNC

Strany 180

DS26519 16-Port T1/E1/J1 Transceiver 260 of 310 10.6 BERT Register Definitions Table 10-25. BERT Register Set ADDRESS NAME DESCRIPTION R/W 1100h

Strany 181

DS26519 16-Port T1/E1/J1 Transceiver 261 of 310 Register Name: BRP1 Register Description: BERT Repetitive Pattern Set Register 1 Register Address: 1

Strany 182

DS26519 16-Port T1/E1/J1 Transceiver 262 of 310 Register Name: BC1 Register Description: BERT Control Register 1 Register Address: 1105h + (10h x (n

Strany 183

DS26519 16-Port T1/E1/J1 Transceiver 263 of 310 Register Name: BC2 Register Description: BERT Control Register 2 Register Address: 1106h + (10h x (n

Strany 184

DS26519 16-Port T1/E1/J1 Transceiver 264 of 310 Register Name: BBC1 Register Description: BERT Bit Count Register 1 Register Address: 1107h + (10h x

Strany 185

DS26519 16-Port T1/E1/J1 Transceiver 265 of 310 Register Name: BEC1 Register Description: BERT Error Count Register 1 Register Address: 110Bh + (10h

Strany 186

DS26519 16-Port T1/E1/J1 Transceiver 266 of 310 Register Name: BLSR Register Description: BERT Latched Status Register Register Address: 110Eh + (10

Strany 187

DS26519 16-Port T1/E1/J1 Transceiver 267 of 310 Register Name: BSIM Register Description: BERT Status Interrupt Mask Register Register Address: 110

Strany 188

DS26519 16-Port T1/E1/J1 Transceiver 268 of 310 11. FUNCTIONAL TIMING 11.1 T1 Receiver Functional Timing Diagrams Figure 11-1. T1 Receive-Side D4 Ti

Strany 189

DS26519 16-Port T1/E1/J1 Transceiver 269 of 310 Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) CHANNEL 23

Strany 190

DS26519 16-Port T1/E1/J1 Transceiver 27 of 310 NAME PIN TYPE FUNCTION RSIG1 D4 RSIG2 B16 RSIG3 J7 RSIG4 R10 RSIG5 U10 RSIG6 V11 RSIG7 H17 RSIG8 V19

Strany 191

DS26519 16-Port T1/E1/J1 Transceiver 270 of 310 Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)

Strany 192

DS26519 16-Port T1/E1/J1 Transceiver 271 of 310 Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode RSERn LSB RSYSCLKn RSYNCn3 FRAM

Strany 193

DS26519 16-Port T1/E1/J1 Transceiver 272 of 310 Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode FR1 C

Strany 194

DS26519 16-Port T1/E1/J1 Transceiver 273 of 310 11.2 T1 Transmitter Functional Timing Diagrams Figure 11-9. T1 Transmit-Side D4 Timing

Strany 195

DS26519 16-Port T1/E1/J1 Transceiver 274 of 310 Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) LSB F M

Strany 196

DS26519 16-Port T1/E1/J1 Transceiver 275 of 310 Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)

Strany 197

DS26519 16-Port T1/E1/J1 Transceiver 276 of 310 Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode TSERn LSB TSYSCLKn TSSYNCIOn

Strany 198

DS26519 16-Port T1/E1/J1 Transceiver 277 of 310 Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode FR

Strany 199

DS26519 16-Port T1/E1/J1 Transceiver 278 of 310 11.3 E1 Receiver Functional Timing Diagrams Figure 11-17. E1 Receive-Side Timing FRAM

Strany 200

DS26519 16-Port T1/E1/J1 Transceiver 279 of 310 Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)

Strany 201

DS26519 16-Port T1/E1/J1 Transceiver 28 of 310 NAME PIN TYPE FUNCTION RCHBLK1/ RCHCLK1 F3 RCHBLK2/ RCHCLK2 G8 RCHBLK3/ RCHCLK3 H5 RCHBLK4/ RCHCLK4 Y

Strany 202

DS26519 16-Port T1/E1/J1 Transceiver 280 of 310 Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode RSERn LSB RSYSCLKn RSYNCn3 FRAM

Strany 203 - Note: See RIM7 for T1 Mode

DS26519 16-Port T1/E1/J1 Transceiver 281 of 310 Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode FR1

Strany 204

DS26519 16-Port T1/E1/J1 Transceiver 282 of 310 11.4 E1 Transmitter Functional Timing Diagrams Figure 11-24. E1 Transmit-Side Timing 1

Strany 205

DS26519 16-Port T1/E1/J1 Transceiver 283 of 310 Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) LSB F

Strany 206

DS26519 16-Port T1/E1/J1 Transceiver 284 of 310 Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode TSERn LSB TSYSCLKnTSSYNCIOn3F

Strany 207

DS26519 16-Port T1/E1/J1 Transceiver 285 of 310 Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode FR

Strany 208

DS26519 16-Port T1/E1/J1 Transceiver 286 of 310 Figure 11-30. E1 G.802 Timing 1 2 3 4 5 6 7 8 9 10111213 14

Strany 209

DS26519 16-Port T1/E1/J1 Transceiver 287 of 310 12. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (exce

Strany 210

DS26519 16-Port T1/E1/J1 Transceiver 288 of 310 12.1 Thermal Characteristics Table 12-4. Thermal Characteristics PARAMETER CONDITIONS MIN TYP MAX UNI

Strany 211

DS26519 16-Port T1/E1/J1 Transceiver 289 of 310 13. AC TIMING CHARACTERISTICS Unless otherwise noted, all timing numbers assume 20pF test load on out

Strany 212

DS26519 16-Port T1/E1/J1 Transceiver 29 of 310 NAME PIN TYPE FUNCTION MICROPROCESSOR INTERFACE A13 C16 A12 F12 A11 A20 A10 G11 A9 H9 A8 A21 A7 F13 A

Strany 213

DS26519 16-Port T1/E1/J1 Transceiver 290 of 310 Figure 13-1. SPI Interface Timing Diagram NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AN

Strany 214

DS26519 16-Port T1/E1/J1 Transceiver 291 of 310 Table 13-2. AC Characteristics—Microprocessor Bus Timing (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS265

Strany 215

DS26519 16-Port T1/E1/J1 Transceiver 292 of 310 Figure 13-2. Intel Bus Read Timing (BTS = 0) t2 t3Address ValidData Validt4t9t5t1

Strany 216

DS26519 16-Port T1/E1/J1 Transceiver 293 of 310 Figure 13-4. Motorola Bus Read Timing (BTS = 1) t2 t6Address Validt4t9t10A[13:0]D[7:0]CSBRWBDSBt7 t

Strany 217

DS26519 16-Port T1/E1/J1 Transceiver 294 of 310 Table 13-3. Receiver AC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26519G; TA = -40°C t

Strany 218

DS26519 16-Port T1/E1/J1 Transceiver 295 of 310 Figure 13-6. Receive Framer Timing—Backplane (T1 Mode) t D1 t D2 RSERn/RSIGn

Strany 219

DS26519 16-Port T1/E1/J1 Transceiver 296 of 310 Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) NOTE 1:

Strany 220

DS26519 16-Port T1/E1/J1 Transceiver 297 of 310 Table 13-4. Transmit AC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26519G; TA = -40°C t

Strany 221

DS26519 16-Port T1/E1/J1 Transceiver 298 of 310 Figure 13-9. Transmit Formatter Timing—Backplane TCLKn TSERn/TSIGn TCH

Strany 222

DS26519 16-Port T1/E1/J1 Transceiver 299 of 310 Figure 13-11. BPCLKn Timing BPCLKn TSSYNCIOn1 t D5 NOTE 1: TSSYNCIOn IS CONFIGURED AS AN OUTPUT (GTC

Strany 223

DS26519 16-Port T1/E1/J1 Transceiver 3 of 310 9.9.7 Maintenance and Alarms ...

Strany 224

DS26519 16-Port T1/E1/J1 Transceiver 30 of 310 NAME PIN TYPE FUNCTION WRB/ RWB R13 Input Write-Read Bar/Read-Write Bar. This active-low signal along

Strany 225

DS26519 16-Port T1/E1/J1 Transceiver 300 of 310 13.2 JTAG Interface Timing Table 13-5. JTAG Interface Timing (VDD = 3.3V ±5%, TA = 0°C to +70°C for

Strany 226

DS26519 16-Port T1/E1/J1 Transceiver 301 of 310 13.3 System Clock AC Characteristics Table 13-6. System Clock AC Characteristics PARAMETER SYMBOL CO

Strany 227

DS26519 16-Port T1/E1/J1 Transceiver 302 of 310 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT The DS26519 IEEE 1149.1 design supports the standard ins

Strany 228

DS26519 16-Port T1/E1/J1 Transceiver 303 of 310 14.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the

Strany 229

DS26519 16-Port T1/E1/J1 Transceiver 304 of 310 for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into t

Strany 230

DS26519 16-Port T1/E1/J1 Transceiver 305 of 310 Figure 14-2. TAP Controller State Diagram 1001111111111110000010000110000SelectDR-ScanCapture DRShift

Strany 231

DS26519 16-Port T1/E1/J1 Transceiver 306 of 310 14.2 Instruction Register The instruction register contains a shift register as well as a latched par

Strany 232

DS26519 16-Port T1/E1/J1 Transceiver 307 of 310 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MAN

Strany 233 - TSYNCINV TSSYNCINV

DS26519 16-Port T1/E1/J1 Transceiver 308 of 310 15. PIN CONFIGURATION 15.1 Pin Configuration—484-Ball HSBGA

Strany 234

DS26519 16-Port T1/E1/J1 Transceiver 309 of 310 16. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current s

Strany 235

DS26519 16-Port T1/E1/J1 Transceiver 31 of 310 NAME PIN TYPE FUNCTION POWER SUPPLIES ATVDD1 C4 ATVDD2 T1 ATVDD3 T3 ATVDD4 AA2 ATVDD5 AA21 ATVDD6 H21

Strany 236

DS26519 16-Port T1/E1/J1 Transceiver 310 of 310 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitr

Strany 237

DS26519 16-Port T1/E1/J1 Transceiver 32 of 310 NAME PIN TYPE FUNCTION ARVSS1 A2 ARVSS2 N3 ARVSS3 W2 ARVSS4 AB1 ARVSS5 AB22 ARVSS6 J20 ARVSS7 G20 ARV

Strany 238

DS26519 16-Port T1/E1/J1 Transceiver 33 of 310 9. FUNCTIONAL DESCRIPTION 9.1 Processor Interface Microprocessor control of the DS26519 is accomplishe

Strany 239

DS26519 16-Port T1/E1/J1 Transceiver 34 of 310 user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master dev

Strany 240

DS26519 16-Port T1/E1/J1 Transceiver 35 of 310 Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 0 A13 LSB MSB SPI_SCLK

Strany 241

DS26519 16-Port T1/E1/J1 Transceiver 36 of 310 generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an o

Strany 242

DS26519 16-Port T1/E1/J1 Transceiver 37 of 310 9.2.2 CLKO Output Clock Generation This clock output is derived from MCLK based upon the setting of t

Strany 243

DS26519 16-Port T1/E1/J1 Transceiver 38 of 310 9.3 Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic low. Th

Strany 244

DS26519 16-Port T1/E1/J1 Transceiver 39 of 310 9.4 Initialization and Configuration 9.4.1 Example Device Initialization and Sequence STEP 1: Reset

Strany 245

DS26519 16-Port T1/E1/J1 Transceiver 4 of 310 13.3 SYSTEM CLOCK AC CHARACTERISTICS ...

Strany 246

DS26519 16-Port T1/E1/J1 Transceiver 40 of 310 9.5 Global Resources All 16 framers share a common microprocessor port and a common MCLK. There are tw

Strany 247

DS26519 16-Port T1/E1/J1 Transceiver 41 of 310 9.7 Device Interrupts Figure 9-11 diagrams the flow of interrupt conditions from their source status b

Strany 248

DS26519 16-Port T1/E1/J1 Transceiver 42 of 310 Figure 9-11. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear 7 Receiv

Strany 249

DS26519 16-Port T1/E1/J1 Transceiver 43 of 310 9.8 System Backplane Interface The DS26519 provides a versatile backplane interface that can be confi

Strany 250

DS26519 16-Port T1/E1/J1 Transceiver 44 of 310 9.8.1.1 Elastic Stores Initialization There are two elastic store initializations that may be used to

Strany 251 - Register Addresses:

DS26519 16-Port T1/E1/J1 Transceiver 45 of 310 9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 enab

Strany 252

DS26519 16-Port T1/E1/J1 Transceiver 46 of 310 9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to e

Strany 253

DS26519 16-Port T1/E1/J1 Transceiver 47 of 310 DS26519 16-Port T1/E1/J1 Transceiver Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz Figure 9

Strany 254

DS26519 16-Port T1/E1/J1 Transceiver 48 of 310 Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz RSERRSIGRSYNCRSYSCLKTSERTSIGTSSYNCTSYSCLKPor

Strany 255

DS26519 16-Port T1/E1/J1 Transceiver 49 of 310 Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz RSERRSIGRSYNCRSYSCLKTSERTSIGTSSYNCTSYSCLKPo

Strany 256

DS26519 16-Port T1/E1/J1 Transceiver 5 of 310 LIST OF FIGURES Figure 7-1. Block Diagram...

Strany 257

DS26519 16-Port T1/E1/J1 Transceiver 50 of 310 Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO

Strany 258

DS26519 16-Port T1/E1/J1 Transceiver 51 of 310 Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO

Strany 259

DS26519 16-Port T1/E1/J1 Transceiver 52 of 310 Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO

Strany 260

DS26519 16-Port T1/E1/J1 Transceiver 53 of 310 Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO

Strany 261

DS26519 16-Port T1/E1/J1 Transceiver 54 of 310 Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO

Strany 262

DS26519 16-Port T1/E1/J1 Transceiver 55 of 310 9.8.3 H.100 (CT Bus) Compatibility The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport

Strany 263

DS26519 16-Port T1/E1/J1 Transceiver 56 of 310 Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode BIT 8 BIT 1 BIT 2RSYNCn1RSYNCn2

Strany 264

DS26519 16-Port T1/E1/J1 Transceiver 57 of 310 9.8.4 Transmit and Receive Channel Blocking Registers The Receive Channel Blocking Registers (RCBR1/R

Strany 265

DS26519 16-Port T1/E1/J1 Transceiver 58 of 310 9.9 Framers The DS26519 framer cores are software selectable for T1, J1, or E1. The receive framer loc

Strany 266

DS26519 16-Port T1/E1/J1 Transceiver 59 of 310 Table 9-12. ESF Framing Mode FRAME NUMBER FRAMING FDL CRC SIGNALING 1 √ 2 CRC1 3 √ 4 0

Strany 267

DS26519 16-Port T1/E1/J1 Transceiver 6 of 310 Figure 11-17. E1 Receive-Side Timing...

Strany 268 - 11. FUNCTIONAL TIMING

DS26519 16-Port T1/E1/J1 Transceiver 60 of 310 FRAME NUMBER Ft Fs SIGNALING 28 C3 (Concentrator Bit) 29 1 30 C4 (Concentrator Bit) A

Strany 269

DS26519 16-Port T1/E1/J1 Transceiver 61 of 310 9.9.2 E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 9-14. Table 9-14. E1

Strany 270

DS26519 16-Port T1/E1/J1 Transceiver 62 of 310 Table 9-15 shows the registers that are related to setting up the framing. Table 9-15. Registers Relat

Strany 271

DS26519 16-Port T1/E1/J1 Transceiver 63 of 310 9.9.3 T1 Transmit Synchronizer The DS26519 transmitter can identify the D4 or ESF frame boundary, as

Strany 272

DS26519 16-Port T1/E1/J1 Transceiver 64 of 310 9.9.4 Signaling The DS26519 supports both software and hardware-based signaling. Interrupts can be gen

Strany 273

DS26519 16-Port T1/E1/J1 Transceiver 65 of 310 9.9.4.1 Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These a

Strany 274 - CHANNEL 23

DS26519 16-Port T1/E1/J1 Transceiver 66 of 310 9.9.4.2 Receive-Signaling Operation There are two methods to access receive-signaling data and provide

Strany 275 - CHANNEL 31

DS26519 16-Port T1/E1/J1 Transceiver 67 of 310 9.9.4.2.6 Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers will be

Strany 276

DS26519 16-Port T1/E1/J1 Transceiver 68 of 310 9.9.4.4 Receive SLC-96 Operation (T1 Mode Only) In an SLC-96-based transmission scheme, the standard

Strany 277

DS26519 16-Port T1/E1/J1 Transceiver 69 of 310 9.9.5 T1 Data Link 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26519 contai

Strany 278

DS26519 16-Port T1/E1/J1 Transceiver 7 of 310 LIST OF TABLES Table 4-1. T1-Related Telecommunications Specifications ...

Strany 279

DS26519 16-Port T1/E1/J1 Transceiver 70 of 310 9.9.5.3 Legacy T1 Transmit FDL It is recommended that the DS26519’s built-in BOC or HDLC controllers

Strany 280

DS26519 16-Port T1/E1/J1 Transceiver 71 of 310 9.9.6 E1 Data Link Table 9-23 shows the registers related to E1 data link. Table 9-23. Registers Rela

Strany 281

DS26519 16-Port T1/E1/J1 Transceiver 72 of 310 9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26519, when operated i

Strany 282 - LSB MSB LSB MSB

DS26519 16-Port T1/E1/J1 Transceiver 73 of 310 Table 9-24 shows some of the registers related to maintenance and alarms. Table 9-24. Registers Relate

Strany 283 - LSB F MSBLSB MSB

DS26519 16-Port T1/E1/J1 Transceiver 74 of 310 9.9.7.1 Status and Information Bit Operation When a particular event has occurred (or is occurring),

Strany 284

DS26519 16-Port T1/E1/J1 Transceiver 75 of 310 9.9.8 Alarms Table 9-25. T1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA AIS (Blue Alarm) (See N

Strany 285

DS26519 16-Port T1/E1/J1 Transceiver 76 of 310 9.9.8.2 Receive RAI Table 9-27 shows the registers related to the receive RAI (Yellow Alarm). Table 9-

Strany 286 - CHANNEL 25

DS26519 16-Port T1/E1/J1 Transceiver 77 of 310 9.9.9 Error Count Registers The DS26519 contains four counters that are used to accumulate line coding

Strany 287 - ABSOLUTE MAXIMUM RATINGS

DS26519 16-Port T1/E1/J1 Transceiver 78 of 310 9.9.9.2 Path Code Violation Count Register (PCVCR) In T1 operation, the Path Code Violation Count Reg

Strany 288 - 12.1 Thermal Characteristics

DS26519 16-Port T1/E1/J1 Transceiver 79 of 310 9.9.10 DS0 Monitoring Function The DS26519 can monitor one DS0 (64kbps) channel in the transmit direc

Strany 289 - With 100pF on all SPI pins

DS26519 16-Port T1/E1/J1 Transceiver 8 of 310 Table 10-2. Global Register Mapping...

Strany 290 - 290 of 310

DS26519 16-Port T1/E1/J1 Transceiver 80 of 310 9.9.11 Transmit Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a pe

Strany 291

DS26519 16-Port T1/E1/J1 Transceiver 81 of 310 9.9.15 T1 Programmable In-Band Loop Code Generator The DS26519 can generate and detect a repeating bi

Strany 292

DS26519 16-Port T1/E1/J1 Transceiver 82 of 310 9.9.16 T1 Programmable In-Band Loop Code Detection The DS26519 can generate and detect a repeating bi

Strany 293

DS26519 16-Port T1/E1/J1 Transceiver 83 of 310 9.9.17 Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by RCR3. Tab

Strany 294 - RSYSCLKn = 2.048MHz

DS26519 16-Port T1/E1/J1 Transceiver 84 of 310 9.10 HDLC Controllers 9.10.1 Receive HDLC Controller This device has an enhanced HDLC controller that

Strany 295

DS26519 16-Port T1/E1/J1 Transceiver 85 of 310 9.10.1.1 HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive H

Strany 296

DS26519 16-Port T1/E1/J1 Transceiver 86 of 310 Figure 9-18. HDLC Message Receive Example Reset Receive HDLC Controller(RHC.6)Configure Receive HDLC C

Strany 297

DS26519 16-Port T1/E1/J1 Transceiver 87 of 310 9.10.2 Transmit HDLC Controller 9.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available Reg

Strany 298

DS26519 16-Port T1/E1/J1 Transceiver 88 of 310 Figure 9-19. HDLC Message Transmit Example Reset Transmit HDLC Controller(THC.5)Configure Transmit HDL

Strany 299 - Figure 13-11. BPCLKn Timing

DS26519 16-Port T1/E1/J1 Transceiver 89 of 310 9.11 Power-Supply Decoupling Table 9-37. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACIT

Strany 300 - 13.2 JTAG Interface Timing

DS26519 16-Port T1/E1/J1 Transceiver 9 of 310 1. DETAILED DESCRIPTION The DS26519 is an 16-port monolithic device featuring independent transceivers

Strany 301

DS26519 16-Port T1/E1/J1 Transceiver 90 of 310 9.12 Line Interface Units (LIUs) The DS26519 has 16 identical LIU transmit and receive front-ends for

Strany 302 - 10kΩ 10kΩ 10k

DS26519 16-Port T1/E1/J1 Transceiver 91 of 310 Figure 9-20. Network Connection—Longitudinal Protection DS26518TTIPnTRINGnRTIPnRRINGnS1S2S3S4S5S6S7S8T

Strany 303

DS26519 16-Port T1/E1/J1 Transceiver 92 of 310 9.12.1 LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of

Strany 304

DS26519 16-Port T1/E1/J1 Transceiver 93 of 310 9.12.2 Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS

Strany 305 - 305 of 310

DS26519 16-Port T1/E1/J1 Transceiver 94 of 310 9.12.2.1 Transmit-Line Pulse Shapes The DS26519 transmitters can be selected individually to meet the

Strany 306 - 14.2 Instruction Register

DS26519 16-Port T1/E1/J1 Transceiver 95 of 310 Figure 9-22. E1 Transmit Pulse Templates 0-0.1-0.20.10.20.30.40.50.60.70.80.91.01.11.20TIME (ns)SCALED

Strany 307 - 14.4 Test Registers

DS26519 16-Port T1/E1/J1 Transceiver 96 of 310 9.12.2.2 Transmit G.703 Section 10 Synchronization Signal The DS26519 can transmit a 2.048MHz square-

Strany 308 - 15. PIN CONFIGURATION

DS26519 16-Port T1/E1/J1 Transceiver 97 of 310 9.12.3 Receiver 9.12.3.1 Receive Internal Termination The DS26519 contains 16 receivers. The terminati

Strany 309 - 16. PACKAGE INFORMATION

DS26519 16-Port T1/E1/J1 Transceiver 98 of 310 The DS26519 uses a digital clock recovery system. The resultant E1, T1 or J1 clock derived from MCLK i

Strany 310

DS26519 16-Port T1/E1/J1 Transceiver 99 of 310 For short-haul mode, the loss-detection thresholds are based on cable loss of 12dB to 18dB for both T1

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