Rainbow-electronics AT83C26 Uživatelský manuál

Features• 5 Smart Card Interfaces– Compliance with ISO 7816, EMV2000, GIE-CB and GSM Standards– Direct Connection to the Smart CardsLogic Level Shifte

107511B–SCR–10/05AT83C26Operational ModesTWI Bus Control The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, madeup

117511B–SCR–10/05AT83C26 Figure 1. Data transfer on TWI busAddress Byte The first byte to send to the device is the address byte. The device controls

127511B–SCR–10/05AT83C26RESET pinThe TWI ADDRESS BYTE is sampled on A2/CK and A1/RST after a rising edge on RESET pin.The delay between the rising edg

137511B–SCR–10/05AT83C26Table 3. SC2 and SC3 shared IOsDCDC ConvertersThe DC/DC A converter is used to provide smart card voltage for the SC1 interfa

147511B–SCR–10/05AT83C26 Figure 4. Clock Block Diagram with Software ActivationCRST controllerCRSTn for SCn interface (n=1, 2)The CRSTn output pin is

157511B–SCR–10/05AT83C26CRSTn for SCn interface (n= 3, 4, 5)The CRSTn output pin is driven by the CARDRSTn bit value (see SCn_CFG2 register).Two modes

167511B–SCR–10/05AT83C26CIO2, CC42, CC82 controller for SC2 interface Figure 8. CIO2, CC42, CC82 Block DiagramThe SC2_FULL bit must be set to use CC4

177511B–SCR–10/05AT83C26Transparent mode arbitration systemThe first between IO and CIO to force a low level becomes the master.The slave signal is gr

187511B–SCR–10/05AT83C26CCLKn and CIOn (n=1 to 5) slew rate controlThree registers SLEW_CTRL_1, SLEW_CTRL_2 and SLEW_CTRL_3 control the slew rate ofth

197511B–SCR–10/05AT83C26Card Presence DetectionCard presence detection for SC1 interfaceThe card presence signal is connected on the CPRES1 pin. The p

27511B–SCR–10/05AT83C26AcronymsTWI: Two Wire InterfacePOR: Power On ResetPFD: Power Fail DetectART: Automatic Reset TransitionATR: Answer To ResetBloc

207511B–SCR–10/05AT83C26DC/DC convertersDC/DC A converterThe DC/DC A converter is controlled by VCARD1[1:0], SHUTDOWNA, ICCADJA, STEPREGA,VCARD_OK1 an

217511B–SCR–10/05AT83C26Figure 9. DC/DC A Converter Initialization ProcedureDC/DC B converterThe DC/DC B converter is controlled by DCDCB register.Th

227511B–SCR–10/05AT83C26The DC/DCB sensitivity to any overflow current can be modified (20%) by using the ICCADJB bit(DC/DCB register).Initialization

237511B–SCR–10/05AT83C26LDO initialization ProcedureWhen the DC/DC B voltage rises the selected voltage (VDCB_OK=1), the card voltage selectionon CVCC

247511B–SCR–10/05AT83C26Activation Sequence Overview (n=1, 2, 3, 4, 5)The activation sequence on SC1 is only available if a card is detected on CPRES1

257511B–SCR–10/05AT83C26 Figure 14. Software activation without automatic control (ARTn bit = 0)Note:– It is assumed that initially VCARDn[1:0], CARD

267511B–SCR–10/05AT83C26the CRSTn signal is not set and the CAPTURE_MSB and CAPTURE_LSB registers contain thevalue of the counter at the arrival of th

277511B–SCR–10/05AT83C26The CRST signal will be equal to 0 during the number of clock cycles programmed inTIMER_MSB and TIMER_LSB. Then, the CRST sign

287511B–SCR–10/05AT83C26• Reset pin going low (SC1, SC2, SC3, SC4, SC5)•Power Fail (VPFDP)It is a self-timed sequence which cannot be interrupted when

297511B–SCR–10/05AT83C26 Figure 18. Power Fail Detection Figure 19. Emergency deactivation sequenceDuring an emergency deactivation, the signals fal

37511B–SCR–10/05AT83C26Pin DescriptionPinout (Top View)VQFP48 Pinout QFN48 Pinout 12345678910111213 14 15 16 1718 19 2021 22 23 2425262728293031323433

307511B–SCR–10/05AT83C26 Figure 20. Transparent Mode DescriptionFull transparent mode on SCn interfaces (n= 3, 4, 5)The transparent mode with A2/CK i

317511B–SCR–10/05AT83C26Several AT83C26 devices can share the same interrupt pin and the micro controller can identifythe interrupt sources by polling

327511B–SCR–10/05AT83C26After the reading and the clear of the interrupt bits, several bits are used to control the status.Table 5. Status bits desc

337511B–SCR–10/05AT83C26Write CommandsThe write commands are:1. General Call Reset: A general call followed by the value 06h has the same effect as a

347511B–SCR–10/05AT83C2610. Write SC5 interface: SC5_CFG0, SC5_CFG2Configuration of SIM/SAM interface 5.11. Write DCDCB config: DCDCB, LDOConfiguratio

357511B–SCR–10/05AT83C26Read CommandAfter a write command, even with a length of 0 byte, the next read operation is performed on thecorresponding byte

367511B–SCR–10/05AT83C26Registers summaryThe table below gives a quick view on AT83C26 registers. Table 8. Smart card 1 interface registersTable 9.

377511B–SCR–10/05AT83C26Table 13. Common registers for SC1/SC2/SC3/SC4/SC5Table 14. Common registers for SC2/SC3/SC4/SC5Table 15. DC/DC B registers

387511B–SCR–10/05AT83C26RegistersReset value = 0x 1000 0000 Table 17. SC1_ CFG0(Config Byte 0 for SC1)7 6 5 4 3 2 1 01 0 ATRERR1 INSERT1 ICARDERR1 VC

397511B–SCR–10/05AT83C26SC1_CFGReset value = 0x X000 1010 Table 18. SC1_CFG1 (Config Byte 1 for SC17 6 5 4 3 2 1 0X ART1 SHUTDOWNA CARDDET1 PULLUP1 C

47511B–SCR–10/05AT83C26SignalsTable 1. Ports Description VQFP48 or QFN48 Pin numberPad Name Pad InternalPower SupplyESD LimitsPad Type Description1 C

407511B–SCR–10/05AT83C26Reset value = 0x 0001 X000Notes: 1. When CKS1 value is changed a special logic insures no glitch occurs on the CCLK1 pin andac

417511B–SCR–10/05AT83C26Reset value = 0x XXX0 XXXX Table 20. SC1_CFG3 (Config Byte 3 for SC1)7 6 5 4 3 2 1 0X X X ICCADJA X X X XBit Number Bit Mnemo

427511B–SCR–10/05AT83C26Reset value = 0x X000 0000 Table 21. SC1_CFG4 (Config Byte 4 for SC1)7 6 5 4 3 2 1 0X DEMBOOSTA1 DEMBOOSTA0 STEPREGA INT_PULL

437511B–SCR–10/05AT83C26_Reset value = 0x 0110 0000 Table 22. SC1_INTERFACE (Interface Byte for SC1)7 6 5 4 3 2 1 00 IODIS1 CKSTOP1 CARDRST1 CARDC81

447511B–SCR–10/05AT83C26Reset value = reset value depends on hardware configurationTable 23. SC1_STATUS (Status Byte for SC1)7 6 5 4 3 2 1 0CC81 CC41

457511B–SCR–10/05AT83C26Reset value = 0x 0000 X000Table 24. SC2_CFG0 ()7 6 5 4 3 2 1 0VCARD_INT2VCARD_OK2ATRERR2 INSERT2 X VCARDERR2 VCARD21 VCARD20B

467511B–SCR–10/05AT83C26Reset value = 0x XX10 1010 Table 25. SC2_CFG1 ()7 6 5 4 3 2 1 0X X SC2_FULL CARDDET2 PULLUP2 CDS22 CDS21 CDS20Bit Number Bit

477511B–SCR–10/05AT83C26Reset value = 0x00001000 Notes: 1. When CKS2 value is changed a special logic insures no glitch occurs on the CCLK2 pin andact

487511B–SCR–10/05AT83C26Reset value = 0x 000X 0000 Table 27. SC3_CFG0()7 6 5 4 3 2 1 0VCARD_INT3 VCARD_OK3 ATRERR3 X X VCARDERR3 VCARD31 VCARD30Bit N

497511B–SCR–10/05AT83C26Reset value = 0x 0X00 1000 Notes: 1. When CKS3 value is changed a special logic insures no glitch occurs on the CCLK3 pin anda

57511B–SCR–10/05AT83C2622 LIA 2kV PWRDC/DCA input.LIA must be tied to VCC pin through an external coil (typically 10µH) and provides the current for t

507511B–SCR–10/05AT83C26Reset value = 0x 000X X000 Table 29. SC4_CFG0()7 6 5 4 3 2 1 0VCARD_INT4 VCARD_OK4 ATRERR4 X X VCARDERR4 VCARD41 VCARD40Bit N

517511B–SCR–10/05AT83C26Reset value = 0x 0X00 1000 Notes: 1. When CKS4 value is changed a special logic insures no glitch occurs on the CCLK4 pin anda

527511B–SCR–10/05AT83C26Reset value = 0x 000X X000 Table 31. SC5_CFG0()7 6 5 4 3 2 1 0VCARD_INT5 VCARD_OK5 ATRERR5 X X VCARDERR5 VCARD51 VCARD50Bit N

537511B–SCR–10/05AT83C26Reset value = 0x 0X00 1000 Notes: 1. When CKS5 value is changed a special logic insures no glitch occurs on the CCLK5 pin anda

547511B–SCR–10/05AT83C26Reset value = 0x 0000 0001 Reset value = 0x 1001 0000 Reset value = 0x 0000 0000 Reset value = 0x 0000 0000 Table 33. TIMER_M

557511B–SCR–10/05AT83C26Reset value = 0x XXXX 1000 Reset value for IOSEL[3:0]= 0x1000 Table 37. IO_SELECT (Selection byte for IO) 7 6 5 4 3 2 1 0X X

567511B–SCR–10/05AT83C26Note: 1. If no input (IO1, IO2, AUX1, AUX2) is selected for a SCIB pin (CIOn, CC4n CC8n), and if thesmart card interface is st

577511B–SCR–10/05AT83C26Reset value = 0x X000 0000 Table 39. INTERFACEB ()7 6 5 4 3 2 1 0X CARDC82 CARDIO5 CARDIO4CARDIO3/CARDC42CARDIO2 DEMBOOSTB1 D

587511B–SCR–10/05AT83C26Reset value = reset value depends on hardware configurationTable 40. STATUSB () - Read Only7 6 5 4 3 2 1 0X CARDIN2 CIO5 CIO

597511B–SCR–10/05AT83C26Reset value = 0x 1111 0010Table 41. ITDIS ()7 6 5 4 3 2 1 0IODIS5 IODIS4 IODIS3 IODIS2 ITDIS5 ITDIS4 ITDIS3 ITDIS2Bit Number

67511B–SCR–10/05AT83C2638 CVSSB GNDDC/DCB input.This pin must be directly connected to the VSS of power supply.39 LIB 2kV PWRDC/DCB input.LIB must be

607511B–SCR–10/05AT83C26Reset value = 0x 0000 0000 Table 42. DCDCB (Config Interface B Byte 2)7 6 5 4 3 2 1 0SHUTDOWNB VDCB_INT VDCB_OK0ICCADJB STEPR

617511B–SCR–10/05AT83C26Reset value = 0x 0000 1111 Table 43. LDO7 6 5 4 3 2 1 0IPLUS5 IPLUS4 IPLUS3 IPLUS2 1 1 1 1Bit Number Bit Mnemonic Description

627511B–SCR–10/05AT83C26Reset value = 0x 1111 1111 Table 44. SLEW_CTRL_1(Slew control for SC1 and SC2)7 6 5 4 3 2 1 0CCLK2_SLEW_CTRL1CCLK2_SLEW_CTRL0

637511B–SCR–10/05AT83C26Reset value = 0x 1111 1111 Table 45. SLEW_CTRL_2 (Slew control for SC3 and SC4)7 6 5 4 3 2 1 0CCLK4_SLEW_CTRL1CCLK4_SLEW_CTRL

647511B–SCR–10/05AT83C26Reset value = 0x XXXX 1111 Table 46. SLEW_CTRL_3 (Slew control for SC5)7 6 5 4 3 2 1 0X X X XCCLK5_SLEW_CTRL1CCLK5_SLEW_CTRL0

657511B–SCR–10/05AT83C26Electrical CharacteristicsAbsolute Maximum Ratings *(**) Exposed die attached pad must be soldered to groundThermal resistor i

667511B–SCR–10/05AT83C26Table 48. Host Interface (IO1, IO2, AUX1, AUX2, CLK, A2/CK, A1/RST, INT)Symbol Parameter Min Typ Max Unit Test ConditionsVILI

677511B–SCR–10/05AT83C26CICC_ovfCard Supply Current Overflow:ICCADJA = 0 (reset value)70 115 200 mARipple on CVCC 60 200 mVWith low ESR capacitance(0.

687511B–SCR–10/05AT83C26TVLHCVCC 0 to valid 200 2000 μs CL = 2.2μFTable 53. Smart Card 2 Class A, 5V (CVCC2) (Continued)Symbol Parameter Min Typ Max

697511B–SCR–10/05AT83C26Ripple on CVCC 30 200 mVSpikes on CVCC VVcardok up Vcardok high level threshold 5 VVcardok down Vcardok low level threshold 4.

77511B–SCR–10/05AT83C26Pad Type DescriptionTo simplify the understanding of Figure 1. to Figure 8., a shortcut is possible by replacing theweak transi

707511B–SCR–10/05AT83C26Table 59. Smart Card 1, 2, 3, 4, 5 Clock (CCLK1, CCLK2, CCLK3, CCLK4, CCLK5)Symbol Parameter Min Typ Max Unit Test Conditions

717511B–SCR–10/05AT83C26tFFall time 100 μsCL = 30pF Class ACL = 30pF Class BCL = 30pF Class CTable 60. Smart Card n I/Os (CIOn, CC4n, CC8n, CRSTn) (

727511B–SCR–10/05AT83C26Table 64. Slew rate on CIOn with CVCCn= 3V (n=1, 2, 3, 4, 5), Mode 2Symbol Parameter Min Typ Max Unit Test ConditionstR/FRise

737511B–SCR–10/05AT83C26Typical Application10µFXTAL1XTAL2VSS4.7µFVSS10µHVSSVSSCard 1INTCLKVSSCRST1CPRES1CIO1, CC41, CC81CCLK1CVCC1LIACVSSAT83C26SCLSDA

747511B–SCR–10/05AT83C26Ordering InformationSamplesPart Number Supply Voltage Temperature Range Package PackingAT83C26-PLTUL 3V to 5.5V Industrial M

757511B–SCR–10/05AT83C26Package DrawingsVQFP48

767511B–SCR–10/05AT83C26QFN48

Printed on recycled paper.7511B–SCR–10/05© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, are registered tradema

87511B–SCR–10/05AT83C26Input/Output with Open Drain Configuration (SDA, SCL, RESET)Figure 3. Input/Output with Open Drain ConfigurationOutput Configu

97511B–SCR–10/05AT83C26Open drain Output with programmable pull-up Configuration (INT)Figure 6. Open Drain Output with programmable pull-upInput Conf