Rainbow-electronics ATA6824 Uživatelský manuál

Features• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors• High Temperature Capability up to 200° C Junction• A Progr

104931C–AUTO–09/06ATA6824 [Preliminary] 5.5 Control Inputs DIR and PWM5.5.1 Pin DIR Logical input to control the direction of the external motor to be

114931C–AUTO–09/06ATA6824 [Preliminary]5.6 VG RegulatorThe VG regulator is used to generate the gate voltage for the low-side driver. Its output volta

124931C–AUTO–09/06ATA6824 [Preliminary] Figure 5-4. Timing of the Drivers The delays tHxLH and tLxLH include the cross conduction time tCC.5.10 Short

134931C–AUTO–09/06ATA6824 [Preliminary]6. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent da

144931C–AUTO–09/06ATA6824 [Preliminary] 7. Thermal ResistanceParameters Symbol Value UnitThermal resistance junction to heat slug Rthjc<5 K/WTherma

154931C–AUTO–09/06ATA6824 [Preliminary]10. Electrical CharacteristicsAll parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°

164931C–AUTO–09/06ATA6824 [Preliminary] 3 Reset and Watchdog3.1VCC threshold voltage level for /RESETVMODE = “H” (VMODE = “L”) 29 VtHRESH4.9 (3.25)VA3

174931C–AUTO–09/06ATA6824 [Preliminary]3.17Internal pull-up resistor at pin /RESET5RPURES5 10 15 kΩ D4 High Voltage Serial Interface4.1 Low-level outp

184931C–AUTO–09/06ATA6824 [Preliminary] 4.13Node has to sustain the current that can flow under this condition. Bus must remain operational under this

194931C–AUTO–09/06ATA6824 [Preliminary]7.4Output peak current at pins L1, L2, switched to LOWVLx = 3VILxL, x = 1, 2100 mA D7.5Output peak current at p

24931C–AUTO–09/06ATA6824 [Preliminary] Figure 1-1. Block Diagram VMODE /RESETMicrocontrollerLogic ControlVCCNCWD12VRegulatorVint 5VRegulatorOTP12 bitO

204931C–AUTO–09/06ATA6824 [Preliminary] 7.17 Fall time low-side driverVVBAT = 13.5VCGx=5 nFtLxf0.5 µs7.18 Rise time low-side driver tLxr0.5 µs7.19Prop

214931C–AUTO–09/06ATA6824 [Preliminary]12. Package Information 11. Ordering InformationExtended Type Number Package RemarksATA6824-PHQW QFN32 Pb-free

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34931C–AUTO–09/06ATA6824 [Preliminary]2. Pin ConfigurationFigure 2-1. Pinning QFN32 Note: YWW Date code (Y = Year - above 2000, WW = week number)ATA6

44931C–AUTO–09/06ATA6824 [Preliminary] 3. General Statement and Conventions• Parameter values given without tolerances are indicative only and not to

54931C–AUTO–09/06ATA6824 [Preliminary]4. Application4.1 General RemarkThis chapter describes the principal application for which the ATA6824 was desig

64931C–AUTO–09/06ATA6824 [Preliminary] 5.1.2 Voltage SupervisorThis block is intended to protect the IC and the external power MOS transistors against

74931C–AUTO–09/06ATA6824 [Preliminary]Figure 5-1. Timing Diagram of the Watchdog Function 5.3.1 Timing SequenceFor example, with an external resistor

84931C–AUTO–09/06ATA6824 [Preliminary] If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms.The watchdog

94931C–AUTO–09/06ATA6824 [Preliminary]Figure 5-3. Definition of Bus Timing Parameters The recessive BUS level is generated from the integrated 30 kΩ p