Rainbow-electronics ATF1516ASL Uživatelský manuál

Procházejte online nebo si stáhněte Uživatelský manuál pro Software Rainbow-electronics ATF1516ASL. Rainbow Electronics ATF1516ASL User Manual Uživatelská příručka

  • Stažení
  • Přidat do mých příruček
  • Tisk
  • Strana
    / 13
  • Tabulka s obsahem
  • KNIHY
  • Hodnocené. / 5. Na základě hodnocení zákazníků
Zobrazit stránku 0
1
High-
performance
EE-based CPLD
ATF1516AS
ATF1516ASL
Preliminary
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
256 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
160, 192, 208 pins
10 ns Maximum Pin-to-pin Delay
Registered Operation Up To 100 MHz
Enhanced Routing Resources
Flexible Logic Macrocell
D/T/Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
Automatic 3 mA Standby for “L” Version (Maximum)
Pin-controlled 4 mA Standby Mode (Typical)
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 160-lead PQFP, 192-pin PGA, and 208-lead RQFP Packages
Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O Pins
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
Edge Controlled Power-down “L”
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs and I/O
Rev. 0994D–09/99
Zobrazit stránku 0
1 2 3 4 5 6 ... 12 13

Shrnutí obsahu

Strany 1 - Enhanced Features

1High-performanceEE-based CPLDATF1516ASATF1516ASLPreliminaryFeatures• High-density, High-performance, Electrically-erasable ComplexProgrammable Logic

Strany 2

ATF1516AS(L)10PCI ComplianceThe ATF1516AS also supports the growing need in theindustry to support the new peripheral component intercon-nect (PCI) in

Strany 3

ATF1516AS(L)11Using “C” Product for IndustrialTo use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to

Strany 4

ATF1516AS(L)12Packaging Information1.218(30.95)1.238(31.45)SQ.008(0.20).016(0.40)PIN 1 ID.0256(0.65) BSC1.098(27.90)1.106(28.10)SQ.127(3.22).157(3.97)

Strany 5

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

Strany 6

ATF1516AS(L)2Block Diagram6 to 12EFGHMNOPLKJI256

Strany 7

ATF1516AS(L)3DescriptionThe ATF1516AS is a high-performance, high-density com-plex programmable logic device (CPLD) that utilizesAtmel’s proven electr

Strany 8

ATF1516AS(L)4Product Terms and Select MUXEach ATF1516AS macrocell has five product terms. Eachproduct term receives as its inputs all signals from bo

Strany 9

ATF1516AS(L)5Programmable Pin-keeper Option for Inputs and I/OsThe ATF1516AS offers the option of programming all inputand I/O pins so that “pin keepe

Strany 10 - ATF1516AS(L)

ATF1516AS(L)6process users may configure the device with the Power-upReset hysteresis set to Large or Small. Atmel POF2JEDusers may select the Large o

Strany 11

ATF1516AS(L)7Input Test Waveforms and Measurement LevelsrR, tF = 1.5 ns typicalOutput AC Test Loads:Note: *Numbers in parenthesis refer to 3.0V operat

Strany 12

ATF1516AS(L)8JTAG-BST OverviewThe JTAG boundary-scan testing is controlled by the TestAccess Port (TAP) controller in the ATF1516AS. Theboundary-scan

Strany 13 - 0994D–09/99/xM

ATF1516AS(L)9BSC Configuration for Macrocell01DQ0101DQDQCaptureDRCaptureDRUpdateDR0101DQDQTDITDIOUTJOEJShiftShiftClockClockModeTDOTDOPin BSCMacrocell

Komentáře k této Příručce

Žádné komentáře