Rainbow-electronics AT17LV040 Uživatelský manuál stáhnout pdf

Features

• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

• Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version

• In-System Programmable (ISP) via Two-Wire Bus

• Simple Interface to SRAM FPGAs

•

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX

, APEX

™

Devices,

Lucent ORCA

FPGAs, Xilinx XC3000

™

, XC4000

™

, XC5200

™

, Spartan

, Virtex

FPGAs

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Very Low-power CMOS EEPROM Process

• Programmable Reset Polarity

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and

44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-

to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-

lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The

AT17LV series Configurators uses a simple serial-access procedure to configure one

or more FPGA devices. The user can select the polarity of the reset function by pro-

gramming four EEPROM bytes. These devices also support a write-protection

mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-

ble to use an 8-lead LAP package instead.

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the

AT17LV512/010/002 devices.

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

Table 1. AT17LV Series Packages

Package

AT17LV65/

AT17LV128/

AT17LV256

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

8-lead LAP Yes Yes Yes

(3)

8-lead PDIP Yes Yes – –

8-lead SOIC Yes

Use 8-lead LAP

(1)

Use 8-lead LAP

(1)

(3)

20-lead PLCC Yes Yes Yes –

20-lead SOIC Yes

(2)

Ye s

(2)

Ye s

(2)

–

44-lead PLCC – – Yes Yes

44-lead TQFP – – Yes Yes

FPGA

Configuration

EEPROM

Memory

AT17LV65

AT17LV128

AT17LV256

AT17LV512

AT17LV010

AT17LV002

AT17LV040

3.3V and 5V

System Support

Rev. 2321D–CNFG–10/02

1 2 3 4 5 6 ... 23 24

Shrnutí obsahu

Strany 1 - Description

1Features• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memorie

Strany 2 - Pin Configuration

10AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02DC CharacteristicsVCC = 3.3V ± 10%Symbol DescriptionAT17LV65/AT17LV128/AT17LV256AT17LV512/AT17LV010A

Strany 3 - 20-lead SOIC

11AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02AC CharacteristicsAC Characteristics when CascadingCERESET/OECLKDATATSCETLCTHCTCACTOETCETOHTHOETSCET

Strany 4

12AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Notes: 1. AC test lead = 50 pF.2. Float delays are measured with 5 pF AC loads. Transition is measur

Strany 5 - POWER ON

13AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Notes: 1. AC test lead = 50 pF.2. Float delays are measured with 5 pF AC loads. Transition is measur

Strany 6

14AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available

Strany 7

15AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Figure 1. Ordering CodePackage Type8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) –

Strany 8

16AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Note: 1. For operating voltage of 5V ±10%, please refer to the 5V ±10% AC and DC Characteristics.Ord

Strany 9 - Operating Conditions

17AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Packaging Information8CN4 – LAP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8C

Strany 10 - 2321D–CNFG–10/02

18AT17LV65/128/256/512/010/002/0402321D–CNFG–10/028P3 – PDIP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.300" Wid

Strany 11

19AT17LV65/128/256/512/010/002/0402321D–CNFG–10/028S1 – SOIC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lead

Strany 12 - = 3.3V ± 10%

2AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Pin Configuration8-lead LAP8-lead SOIC8-lead PDIP20-lead PLCCNotes: 1. This pin is only available on

Strany 13

20AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0220J – PLCC 2325 Orchard Parkway San Jose, CA 95131RTITLEDRAWING NO.REV. Notes: 1. This package c

Strany 14 - 2. Airflow = 0 ft/min

21AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0220S2 – SOIC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 20S2, 20-lead, 0.300"

Strany 15 - AT17LV65A-10PC

22AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0244A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm

Strany 16 - Ordering Information

23AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0244J – PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1

Strany 17 - Side View

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

Strany 18 - End View

3AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0220-lead SOIC(1)Note: 1. This pinout only applies to AT17LV65/128/256 devices.20-lead SOIC(1)Note: 1.

Strany 19

4AT17LV65/128/256/512/010/002/0402321D–CNFG–10/0244 PLCC44 TQFPNote: 1. This pin is only available on AT17LV002 devices.789101112131415161739383736353

Strany 20 - 20J – PLCC

5AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Block DiagramNotes: 1. This pin is only available on AT17LV65/128/256 devices.2. This pin is only ava

Strany 21

6AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02DATA Three-state DATA output for configuration. Open-collector bi-directional pin forprogramming.CLK

Strany 22 - 44A – TQFP

7AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment theaddress coun

Strany 23 - 44J – PLCC

8AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02FPGA Master Serial Mode SummaryThe I/O and logic functions of any SRAM-based FPGA are established by

Strany 24

9AT17LV65/128/256/512/010/002/0402321D–CNFG–10/02Absolute Maximum Ratings*Operating Temperature......... -40°C to +85°C*NOT

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