Rainbow-electronics AT25256A Uživatelský manuál

18-lead SOIC12348765CSSOWPGNDVCCHOLDSCKSIFeatures• Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• Medium-voltag

10AT25128A/256A [Preliminary]3404A–SEEPR–10/03Timing Diagrams (for SPI Mode 0 (0, 0))Synchronous Data TimingWREN TimingWRDI TimingSOVOHVOLHI-ZHI-ZtVVA

11AT25128A/256A [Preliminary]3404A–SEEPR–10/03RDSR TimingWRSR TimingREAD TimingCSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA OUTMSBHIGH IMPEDAN

12AT25128A/256A [Preliminary]3404A–SEEPR–10/03WRITE TimingHOLD Timing SOSCKHOLDtCDtHDtHZtLZtCDtHDCS

13AT25128A/256A [Preliminary]3404A–SEEPR–10/03 AT25128A Ordering Information Ordering Code Package Operation RangeAT25128A-10PA-5.0CAT25128AN-10SA-5.0

14AT25128A/256A [Preliminary]3404A–SEEPR–10/03 AT25256A Ordering InformationOrdering Code Package Operation RangeAT25256A-10PA-5.0CAT25256AN-10SA-5.0C

15AT25128A/256A [Preliminary]3404A–SEEPR–10/03Packaging Information8P3 – PDIP 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-le

16AT25128A/256A [Preliminary]3404A–SEEPR–10/038S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. Note:10/3/

17AT25128A/256A [Preliminary]3404A–SEEPR–10/038S2 – EIAJ SOIC 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8S2, 8-lead, 0.209"

Printed on recycled paper.3404A–SEEPR–10/03 xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly

2AT25128A/256A [Preliminary]3404A–SEEPR–10/03The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consist

3AT25128A/256A [Preliminary]3404A–SEEPR–10/03Note: 1. This parameter is characterized and is not 100% tested.Note: 1. VIL and VIH max are reference on

4AT25128A/256A [Preliminary]3404A–SEEPR–10/03Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.AC

5AT25128A/256A [Preliminary]3404A–SEEPR–10/03Serial Interface DescriptionMASTER: The device that generates the serial clock.SLAVE: Because the Serial

6AT25128A/256A [Preliminary]3404A–SEEPR–10/03SPI Serial Interface Functional DescriptionThe AT25128A/256A is designed to interface directly with the

7AT25128A/256A [Preliminary]3404A–SEEPR–10/03WRITE ENABLE (WREN): The device will power-up in the write disable state when VCCis applied. All programm

8AT25128A/256A [Preliminary]3404A–SEEPR–10/03The WRSR instruction also allows the user to enable or disable the write protect (WP)pin through the use

9AT25128A/256A [Preliminary]3404A–SEEPR–10/03The AT25128A/256A is capable of a 64-byte PAGE WRITE operation. After each byte ofdata is received, the s