Rainbow-electronics AT25DF081 Uživatelský manuál

Features• Single 1.65V - 1.95V Supply• Serial Peripheral Interface (SPI) Compatible– Supports SPI Modes 0 and 3• 66 MHz Maximum Clock Frequency• Flexi

103674E–DFLASH–8/08AT25DF081Figure 8-1. Byte ProgramFigure 8-2. Page Program8.2 Block EraseA block of 4K-, 32K-, or 64K-bytes can be erased (all bits

113674E–DFLASH–8/08AT25DF081If the address specified by A23-A0 points to a memory location within a sector that is in the pro-tected state, then the B

123674E–DFLASH–8/08AT25DF081ter be polled rather than waiting the tCHPEtime to determine if the device has finished erasing. Atsome point before the e

133674E–DFLASH–8/08AT25DF0819.2 Write DisableThe Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-ister to th

143674E–DFLASH–8/08AT25DF081A0 will be set to the logical “1” state, and the sector itself will then be protected from programand erase operations. In

153674E–DFLASH–8/08AT25DF081As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Pro-tection Registers can thems

163674E–DFLASH–8/08AT25DF081Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector ProtectionRegisters are not locked

173674E–DFLASH–8/08AT25DF081If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-tect, then the system can

183674E–DFLASH–8/08AT25DF081Figure 9-5. Read Sector Protection Register9.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked to

193674E–DFLASH–8/08AT25DF081The tables below detail the various protection and locking states of the device.Note: 1. “n” represents a sector numberTab

23674E–DFLASH–8/08AT25DF081The AT25DF081 also offers a sophisticated method for protecting individual sectors againsterroneous or malicious program an

203674E–DFLASH–8/08AT25DF08110. Status Register Commands10.1 Read Status RegisterThe Status Register can be read to determine the device’s ready/busy

213674E–DFLASH–8/08AT25DF08110.1.1 SPRL BitThe SPRL bit is used to control whether the Sector Protection Registers can be modified or not.When the SPR

223674E–DFLASH–8/08AT25DF081• Write Disable operation completes successfully• Write Status Register operation completes successfully or aborts• Protec

233674E–DFLASH–8/08AT25DF081The complete one byte of data must be clocked into the device before the CS pin is deasserted,and theCS pin must be deasse

243674E–DFLASH–8/08AT25DF081Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and putthe SO pin into a high-impedanc

253674E–DFLASH–8/08AT25DF08111.2 Deep Power-DownDuring normal operation, the device will be placed in the standby mode to consume less poweras long as

263674E–DFLASH–8/08AT25DF08111.3 Resume from Deep Power-DownIn order exit the Deep Power-Down mode and resume normal device operation, the Resumefrom

273674E–DFLASH–8/08AT25DF08111.4 HoldThe HOLD pin is used to pause the serial communication with the device without having to stopor reset the clock s

283674E–DFLASH–8/08AT25DF08112. Electrical Specifications12.1 Absolute Maximum Ratings*Temperature Under Bias ... -55C to

293674E–DFLASH–8/08AT25DF081Notes: 1. Not 100% tested (value guaranteed by design and characterization).2. 15 pF load at 66 MHz, 30 pF load at 60 MHz.

33674E–DFLASH–8/08AT25DF0812. Pin Descriptions and PinoutsTable 2-1. Pin DescriptionsSymbol Name and FunctionAssertedState TypeCSCHIP SELECT: Assertin

303674E–DFLASH–8/08AT25DF081Notes: 1. Not 100% tested (value guaranteed by design and characterization).12.7 Input Test Waveforms and Measurement Leve

313674E–DFLASH–8/08AT25DF08113. AC WaveformsFigure 13-1. Serial Input TimingFigure 13-2. Serial Output TimingFigure 13-3.HOLD Timing – Serial InputCSS

323674E–DFLASH–8/08AT25DF081Figure 13-4. HOLD Timing – Serial OutputFigure 13-5. WP Timing for Write Status Register Command When SPRL = 1CSSISCKSOtHH

333674E–DFLASH–8/08AT25DF08114. Ordering Information14.1 Ordering Code Detail – Standard Package OfferingsNotes: 1. The shipping carrier option code i

343674E–DFLASH–8/08AT25DF08114.3 Ordering Code Detail – Wafer Level OptionsNotes: 1. Die/wafer carrier option code is not marked on devices.2. Please

353674E–DFLASH–8/08AT25DF08115. Packaging Information15.1 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINN

363674E–DFLASH–8/08AT25DF08115.2 8MA1 – UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YFG D 8MA1, 8-pad (5 x 6 x 0.6

373674E–DFLASH–8/08AT25DF08116. Revision HistoryRevision Level – Release Date HistoryA – September 2007 Initial releaseB – October 2007Changed part nu

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

43674E–DFLASH–8/08AT25DF0813. Block Diagram4. Memory ArrayTo provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four

53674E–DFLASH–8/08AT25DF081Figure 4-1. Memory Architecture DiagramInternal Sectoring for 64KB 32KB 4KB 1-256 ByteSector Protection Block Erase Block E

63674E–DFLASH–8/08AT25DF0815. Device OperationThe AT25DF081 is controlled by a set of instructions that are sent from a host controller, com-monly ref

73674E–DFLASH–8/08AT25DF081Table 6-1. Command ListingCommand Opcode Address Bytes Dummy Bytes Data BytesRead CommandsRead Array 0Bh 0000 1011 3 1 1+Re

83674E–DFLASH–8/08AT25DF0817. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream of data fromthe d

93674E–DFLASH–8/08AT25DF0818. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page Program command allows anywhere from a single byte of data