Rainbow-electronics AT25DQ321 Uživatelský manuál

8718D–DFLASH–12/2012Features Single 2.7V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI Modes 0 and 3 Supports RapidS™ o

10AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 7-2. Read Array – 0Bh OpcodeFigure 7-3. Read Array – 03h OpcodeSOSISCKCSMSB MSB23100000101167541011

11AT25DQ321 [DATASHEET]8718D–DFLASH–12/20127.2 Dual-Output Read ArrayThe Dual-Output Read Array command is similar to the standard Read Array command

12AT25DQ321 [DATASHEET]8718D–DFLASH–12/20127.3 Quad-Output Read ArrayThe Quad-Output Read Array command is similar to the Dual-Output Read Array comm

13AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page Program command allows anywhere from a sin

14AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 8-1. Byte ProgramFigure 8-2. Page ProgramSOSISCKCSMSB MSB231000000010675410119812 3937 3833 3635343

15AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.2 Dual-Input Byte/Page ProgramThe Dual-Input Byte/Page Program command is similar to the standard Byte/P

16AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 8-3. Dual-Input Byte ProgramFigure 8-4. Dual-Input Page ProgramSCKMSB MSB231010100010675410119812 3

17AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.3 Quad-Input Byte/Page ProgramThe Quad-Input Byte/Page Program command is similar to the Dual-Input Byte

18AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 8-5. Quad-Input Byte ProgramFigure 8-6. Quad-Input Page ProgramI/O0(SI)SCKI/O1(SO)I/O2(WP)I/O3(HOLD

19AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.4 Block EraseA block of 4, 32, or 64 KB can be erased (all bits set to the Logical 1 state) in a single

2AT25DQ321 [DATASHEET]8718D–DFLASH–12/20121. DescriptionThe AT25DQ321 is a serial interface Flash memory device designed for use in a wide variety of

20AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.5 Chip EraseThe entire memory array can be erased in a single operation by using the Chip Erase command.

21AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.6 Program/Erase SuspendIn some code plus data storage applications, it is often necessary to process cer

22AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Table 8-1. Operations Allowed and Not Allowed During a Program or Erase SuspendFigure 8-9. Program/Erase S

23AT25DQ321 [DATASHEET]8718D–DFLASH–12/20128.7 Program/Erase ResumeThe Program/Erase Resume command allows a suspended program or erase operation to

24AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129. Protection Commands and Features9.1 Write EnableThe Write Enable command is used to set the Write Enabl

25AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.2 Write DisableThe Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status

26AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.3 Protect SectorEvery physical 64KB sector of the device has a corresponding single-bit Sector Protectio

27AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.4 Unprotect SectorIssuing the Unprotect Sector command to a particular sector address will reset the cor

28AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.5 Global Protect/UnprotectThe Global Protect and Global Unprotect features can work in conjunction with

29AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Table 9-2. Valid SPRL and Global Protect/Unprotect ConditionsWPStateCurrentSPRLValueNew Write StatusRegist

3AT25DQ321 [DATASHEET]8718D–DFLASH–12/20122. Pin Descriptions and PinoutsTable 2-1. Pin Descriptions Symbol Name and FunctionAssertedStateTypeCSChip

30AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.6 Read Sector Protection RegistersThe Sector Protection Registers can be read to determine the current s

31AT25DQ321 [DATASHEET]8718D–DFLASH–12/20129.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked to the memory array itself and

32AT25DQ321 [DATASHEET]8718D–DFLASH–12/201210. Security Commands10.1 Sector LockdownCertain applications require that portions of the Flash memory ar

33AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 10-1. Sector LockdownSOSISCKCSMSB MSB2310001100116754983937 3833 36353431 3229 30OpcodeHigh-impedan

34AT25DQ321 [DATASHEET]8718D–DFLASH–12/201210.2 Freeze Sector Lockdown StateThe current sector lockdown state can be permanently frozen so that no fu

35AT25DQ321 [DATASHEET]8718D–DFLASH–12/201210.3 Read Sector Lockdown RegistersThe Sector Lockdown Registers can be read to determine the current lock

36AT25DQ321 [DATASHEET]8718D–DFLASH–12/201210.4 Program OTP Security RegisterThe device contains a specialized OTP (One-Time Programmable) Security R

37AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012The three address bytes and at least one complete byte of data must be clocked into the device before the

38AT25DQ321 [DATASHEET]8718D–DFLASH–12/201210.5 Read OTP Security RegisterThe OTP Security Register can be sequentially read in a similar fashion to

39AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211. Status Register Commands11.1 Read Status RegisterThe 2-byte Status Register can be read to determine t

4AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 2-1. Pin ConfigurationsWP (I/O2)Write Protect (I/O2): The WP# pin controls the hardware locking fea

40AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Registe

41AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.1.2 EPE BitThe EPE bit indicates whether the last erase or program operation completed successfully or

42AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.1.6 RSTE BitThe RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the Lo

43AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.2 Write Status Register Byte 1The Write Status Register Byte 1 command is used to modify the SPRL bit o

44AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.3 Write Status Register Byte 2The Write Status Register Byte 2 command is used to modify the RSTE and S

45AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.4 Read Configuration RegisterThe non-volatile Configuration Register can be read to determine if the Qu

46AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.4.1 QE BitThe QE bit is used to control whether the Quad-Input Byte/Page Program and Quad-Output Read A

47AT25DQ321 [DATASHEET]8718D–DFLASH–12/201211.5 Write Configuration RegisterThe Write Configuration Register command is used to modify the QE bit of

48AT25DQ321 [DATASHEET]8718D–DFLASH–12/201212. Other Commands and Functions12.1 ResetIn some applications, it may be necessary to prematurely termina

49AT25DQ321 [DATASHEET]8718D–DFLASH–12/201212.2 Read Manufacturer and Device IDIdentification information can be read from the device to enable syste

5AT25DQ321 [DATASHEET]8718D–DFLASH–12/20123. Block DiagramFigure 3-1. Block DiagramFlashMemoryArrayY-GatingCSSCKNote: I/O3-0 pin naming convention i

50AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 12-2. Read Manufacturer and Device IDSOSISCKCS609Fh87 46Opcode1Fh 86h 00h 01h 00hManufacturer ID De

51AT25DQ321 [DATASHEET]8718D–DFLASH–12/201212.3 Deep Power-DownDuring normal operation, the device will be placed in the standby mode to consume less

52AT25DQ321 [DATASHEET]8718D–DFLASH–12/201212.4 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal device operati

53AT25DQ321 [DATASHEET]8718D–DFLASH–12/201212.5 HoldThe HOLD pin is used to pause the serial communication with the device without having to stop or

54AT25DQ321 [DATASHEET]8718D–DFLASH–12/201213. Electrical Specifications13.1 Absolute Maximum Ratings*13.2 DC and AC Operating Range13.3 DC Character

55AT25DQ321 [DATASHEET]8718D–DFLASH–12/201213.4 AC Characteristics – Maximum Clock Frequencies13.5 AC Characteristics – All Other ParametersNotes: 1.

56AT25DQ321 [DATASHEET]8718D–DFLASH–12/201213.6 Program and Erase CharacteristicsNotes: 1. Maximum values indicate worst-case performance after 100,0

57AT25DQ321 [DATASHEET]8718D–DFLASH–12/201214. AC WaveformsFigure 14-1. Serial Input TimingFigure 14-2. Serial Output TimingFigure 14-3.WP Timing for

58AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Figure 14-4. HOLD Timing – Serial InputFigure 14-5.HOLD Timing – Serial OutputSOSIHOLDSCKCStHHHtHLStHLHtHH

59AT25DQ321 [DATASHEET]8718D–DFLASH–12/201215. Ordering Information15.1 Ordering Code Detail15.2 Green Package Options (Pb/Halide-free/RoHS-compliant

6AT25DQ321 [DATASHEET]8718D–DFLASH–12/20124. Memory ArrayTo provide the greatest flexibility, the memory array of the AT25DQ321 can be erased in four

60AT25DQ321 [DATASHEET]8718D–DFLASH–12/201216. Packaging Information16.1 8S2 – 8-lead EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:con

61AT25DQ321 [DATASHEET]8718D–DFLASH–12/201216.2 8MA1 – 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YFG D 8M

62AT25DQ321 [DATASHEET]8718D–DFLASH–12/201216.3 16S – 16-lead SOICDRAWING NO. REV. TITLEPackage Drawing Contact:[email protected]: 1. Th

63AT25DQ321 [DATASHEET]8718D–DFLASH–12/201217. Revision HistoryDoc. Rev. Date Comments8718D 12/2012 Update 8S1 JEDEC SOIC to 8S2 EIAJ SOIC package op

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

7AT25DQ321 [DATASHEET]8718D–DFLASH–12/20125. Device OperationThe AT25DQ321 is controlled by a set of instructions that are sent from a host controlle

8AT25DQ321 [DATASHEET]8718D–DFLASH–12/2012Table 6-1. Command Listing Command OpcodeClockFrequencyAddressBytesDummyBytesDataBytesRead CommandsRead Arr

9AT25DQ321 [DATASHEET]8718D–DFLASH–12/20127. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream o