Rainbow-electronics AT45DB321D Uživatelský manuál

Features•Single 2.7V - 3.6V Supply•RapidS™ Serial Interface: 66 MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3•User Configurable Page Size–

103597J–DFLASH–4/08AT45DB321D7.6 Sector EraseThe Sector Erase command can be used to individually erase any sector in the main memory.There are 64 sec

113597J–DFLASH–4/08AT45DB321DThe WP pin can be asserted while the device is erasing, but protection will not be activated untilthe internal erase cycl

123597J–DFLASH–4/08AT45DB321D8.1 Software Sector Protection8.1.1 Enable Sector Protection CommandSectors specified for protection in the Sector Protec

133597J–DFLASH–4/08AT45DB321D9. Hardware Controlled ProtectionSectors specified for protection in the Sector Protection Register and the Sector Protec

143597J–DFLASH–4/08AT45DB321D9.1 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sectors are to be protected or u

153597J–DFLASH–4/08AT45DB321D9.1.1 Erase Sector Protection Register CommandIn order to modify and change the values of the Sector Protection Register,

163597J–DFLASH–4/08AT45DB321DAfter the last data byte has been clocked in, the CS pin must be deasserted to initiate the inter-nally self-timed progra

173597J–DFLASH–4/08AT45DB321D9.1.3 Read Sector Protection Register CommandTo read the Sector Protection Register, the CS pin must first be asserted. O

183597J–DFLASH–4/08AT45DB321D10. Security Features10.1 Sector LockdownThe device incorporates a Sector Lockdown mechanism that allows each individual

193597J–DFLASH–4/08AT45DB321D10.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 64 bytes of data, as show

23597J–DFLASH–4/08AT45DB321Dsequentially access its data. The simple sequential access dramatically reduces active pincount, facilitates hardware layo

203597J–DFLASH–4/08AT45DB321D10.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes suchas unique dev

213597J–DFLASH–4/08AT45DB321D10.2.2 Reading the Security RegisterThe Security Register can be read by first asserting the CS pin and then clocking in

223597J–DFLASH–4/08AT45DB321D11.2 Main Memory Page to Buffer CompareA page of data in the main memory can be compared to the data in buffer 1 or buffe

233597J–DFLASH–4/08AT45DB321D11.4 Status Register ReadThe status register can be used to determine the device’s ready/busy status, page size, a MainMe

243597J–DFLASH–4/08AT45DB321D12. Deep Power-downAfter initial power-up, the device will default in standby mode. The Deep Power-down commandallows the

253597J–DFLASH–4/08AT45DB321D13. “Power of 2” Binary Page Size Option“Power of 2” binary page size Configuration Register is a user-programmable nonvo

263597J–DFLASH–4/08AT45DB321D14. Manufacturer and Device ID ReadIdentification information can be read from the device to enable systems to electronic

273597J–DFLASH–4/08AT45DB321DNote: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufac

283597J–DFLASH–4/08AT45DB321DGroup D commands consist of:1. Erase Sector Protection Register2. Program Sector Protection Register3. Sector Lockdown4.

293597J–DFLASH–4/08AT45DB321DNote: 1. These legacy commands are not recommended for new designs.Table 15-3. Protection and Security CommandsCommand Op

33597J–DFLASH–4/08AT45DB321DTable 2-1. Pin ConfigurationsSymbol Name and FunctionAsserted State TypeCSChip Select: Asserting the CS pin selects the de

303597J–DFLASH–4/08AT45DB321DNotes: x = Don’t CareTable 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512 Bytes)Page Size = 512 b

313597J–DFLASH–4/08AT45DB321DNotes: P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t CareTable 15-7. Detailed Bit-level Addressing Sequence

323597J–DFLASH–4/08AT45DB321D16. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devicew

333597J–DFLASH–4/08AT45DB321D18. Electrical SpecificationsNotes: 1. ICC1 during a buffer read is 20 mA maximum @ 20 MHz.2. All inputs are 5 volts tole

343597J–DFLASH–4/08AT45DB321DTable 18-4. AC Characteristics – RapidS/Serial InterfaceSymbol ParameterAT45DB321D Min Typ Max UnitsfSCKSCK Frequency 66

353597J–DFLASH–4/08AT45DB321D19. Input Test Waveforms and Measurement LevelstR, tF < 2 ns (10% to 90%)20. Output Test Load21. AC WaveformsSix diffe

363597J–DFLASH–4/08AT45DB321D21.1 Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66 MHz)21.2 Waveform 2 – SPI Mode 3 Compatible (for freque

373597J–DFLASH–4/08AT45DB321D21.5 Utilizing the RapidS™ FunctionTo take advantage of the RapidS function's ability to operate at higher clock fre

383597J–DFLASH–4/08AT45DB321D21.6 Reset TimingNote: The CS signal should be in the high state before the RESET signal is deasserted.21.7 Command Seque

393597J–DFLASH–4/08AT45DB321D22. Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.22.1 Buffe

43597J–DFLASH–4/08AT45DB321D3. Block Diagram4. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB321D is divided into three le

403597J–DFLASH–4/08AT45DB321D23. Read OperationsThe following block diagram and waveforms illustrate the various read sequences available.23.1 Main Me

413597J–DFLASH–4/08AT45DB321D23.3 Buffer Read24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 324.1 Continuous Array Read (L

423597J–DFLASH–4/08AT45DB321D24.3 Continuous Array Read (Low Frequency: Opcode 03H)24.4 Main Memory Page Read (Opcode: D2H)24.5 Buffer Read (Opcode D4

433597J–DFLASH–4/08AT45DB321D24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)24.7 Read Sector Protection Register (Opcode 32H)24.8 Read Sector Lock

443597J–DFLASH–4/08AT45DB321D24.9 Read Security Register (Opcode 77H)24.10 Status Register Read (Opcode D7H)24.11 Manufacturer and Device Read (Opcode

453597J–DFLASH–4/08AT45DB321D25. Auto Page Rewrite FlowchartFigure 25-1. Algorithm for Programming or Reprogramming of the Entire Array SequentiallyNo

463597J–DFLASH–4/08AT45DB321DFigure 25-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of a DataFlash sector m

473597J–DFLASH–4/08AT45DB321D26. Ordering Information26.1 Ordering Code DetailNotes: 1. The shipping carrier option is not marked on the devices.2. St

483597J–DFLASH–4/08AT45DB321D27. Packaging Information27.1 8M1-A – MLF (VDFN) 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8M1-A,

493597J–DFLASH–4/08AT45DB321D27.2 8MW – MLF (VDFN) 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8MW, 8-pad, 8 x 6 x 1.0 mm Body, V

53597J–DFLASH–4/08AT45DB321D5. Device OperationThe device operation is controlled by instructions from the host processor. The list of instructionsand

503597J–DFLASH–4/08AT45DB321D27.3 8S2 – EIAJ SOIC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8S2, 8-lead, 0.209" Body, Plastic

513597J–DFLASH–4/08AT45DB321D27.4 28T – TSOP, Type 1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 28T, 28-lead (8 x 13.4 mm) Plast

523597J–DFLASH–4/08AT45DB321D28. Revision HistoryRevision Level – Release Date HistoryA – November 2005 Initial ReleaseB – January 2006Added 6 x 5 mm

533597J–DFLASH–4/08AT45DB321D29. Errata29.1 Chip Erase29.1.1 IssueIn a certain percentage of units, the Chip Erase feature may not function correctly

3597J–DFLASH–4/08Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asi

63597J–DFLASH–4/08AT45DB321DContinuous Array Read, the device will continue reading at the beginning of the next page withno delays incurred during th

73597J–DFLASH–4/08AT45DB321Dduring the page boundary crossover (the crossover from the end of one page to the beginning ofthe next page). When the las

83597J–DFLASH–4/08AT45DB321D7. Program and Erase Commands7.1 Buffer WriteData can be clocked in from the input pin (SI) into either buffer 1 or buffer

93597J–DFLASH–4/08AT45DB321D7.4 Page EraseThe Page Erase command can be used to individually erase any page in the main memory arrayallowing the Buffe