Rainbow-electronics DS26503 Uživatelský manuál

1 of 123 REV: 070904 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

DS26503 T1/E1/J1 BITS Element 10 of 123 Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.

DS26503 T1/E1/J1 BITS Element 100 of 123 Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchang

DS26503 T1/E1/J1 BITS Element 101 of 123 Figure 16-2. TAP Controller State Diagram 1001111111111110000010000110000

DS26503 T1/E1/J1 BITS Element 102 of 123 16.1 Instruction Register The instruction register contains a shift register as well as a latched parallel

DS26503 T1/E1/J1 BITS Element 103 of 123 IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification te

DS26503 T1/E1/J1 BITS Element 104 of 123 Table 16-4. Boundary Scan Control Bits CELL # NAME TYPE CONTROL CELL 0 AD1 Output3 1 1 AD1_7_CTRL Control

DS26503 T1/E1/J1 BITS Element 105 of 123 CELL # NAME TYPE CONTROL CELL 28 TPOSO observe_only 29 TNEGO observe_only 30 TCLKO observe_only 31 TCL

DS26503 T1/E1/J1 BITS Element 106 of 123 17. FUNCTIONAL TIMING DIAGRAMS 17.1 Processor Interface 17.1.1 Parallel Port Mode See the AC Timing sectio

DS26503 T1/E1/J1 BITS Element 107 of 123 Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 Figure 17-5. SPI Serial Port

DS26503 T1/E1/J1 BITS Element 108 of 123 Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 Figure 17-8. SPI Serial Po

DS26503 T1/E1/J1 BITS Element 109 of 123 18. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………

DS26503 T1/E1/J1 BITS Element 11 of 123 Table 2-3. E1-Related Telecommunications Specifications (continued) (ETSI) “Business Telecommunications (BT)

DS26503 T1/E1/J1 BITS Element 110 of 123 Table 18-5. DC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26503L; VDD = 3.3V ±5%, TA = -40°C

DS26503 T1/E1/J1 BITS Element 111 of 123 19. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all othe

DS26503 T1/E1/J1 BITS Element 112 of 123 Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) Figure 19-2. Intel Bus Write Tim

DS26503 T1/E1/J1 BITS Element 113 of 123 Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) t ASD ASHPW t t ASL AHLtCSt ASL ttt DSWDHW t CH

DS26503 T1/E1/J1 BITS Element 114 of 123 19.2 Nonmultiplexed Bus Table 19-2. AC Characteristics, Non-Mux Parallel Port (VDD = 3.3V ±5%, TA = 0°C to

DS26503 T1/E1/J1 BITS Element 115 of 123 Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) Figure 19-5. Intel Bus Write

DS26503 T1/E1/J1 BITS Element 116 of 123 Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) Figure 19-7. Motorola B

DS26503 T1/E1/J1 BITS Element 117 of 123 19.3 Serial Bus Table 19-3. AC Characteristics, Serial Bus (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26503

DS26503 T1/E1/J1 BITS Element 118 of 123 Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 Figure 19-9. SPI I

DS26503 T1/E1/J1 BITS Element 119 of 123 19.4 Receive Side AC Characteristics Table 19-4. Receive Side AC Characteristics (VDD = 3.3V ±5%, TA = 0°

DS26503 T1/E1/J1 BITS Element 12 of 123 3. BLOCK DIAGRAMS Figure 3-1. Block Diagram RX LIURX LIUT1/E1 SSM FRAMERCLOCK- DATATX LIUT1/E1 SSMFORMATTE

DS26503 T1/E1/J1 BITS Element 120 of 123 Figure 19-10. Receive Timing, T1/E1 t D1 t D2 RSER RSRCLK E1 = MSB of Channel 1T1 = F-Bit

DS26503 T1/E1/J1 BITS Element 121 of 123 19.5 Transmit Side AC Characteristics Table 19-5. Transmit Side AC Characteristics (VDD = 3.3V ±5%, TA = -

DS26503 T1/E1/J1 BITS Element 122 of 123 Figure 19-11. Transmit Timing, T1/E1 20. REVISION HISTORY REVISION DESCRI

DS26503 T1/E1/J1 BITS Element 123 of 123 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entir

DS26503 T1/E1/J1 BITS Element 13 of 123 Figure 3-2. Loopback Mux Diagram Figure 3-3. Transmit PLL Clock Mux Diagram TX P

DS26503 T1/E1/J1 BITS Element 14 of 123 Figure 3-4. Master Clock PLL Diagram PRE-SCALERDIVIDE BY 1, 2, 4,OR 8MCLK PIN2.048MHz to1.544MHz PLL

DS26503 T1/E1/J1 BITS Element 15 of 123 4. PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE FUNCTION PLL_OUT O Transmit PLL Output. 1544kHz, 2

DS26503 T1/E1/J1 BITS Element 16 of 123 4.3 Receive Side NAME TYPE FUNCTION RCLK O Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), or 6312 k

DS26503 T1/E1/J1 BITS Element 17 of 123 4.4 Controller Interface NAME TYPE FUNCTION INT/ JACKS I/O Interrupt/JA Clock Source Select 1 INT: Flags h

DS26503 T1/E1/J1 BITS Element 18 of 123 NAME TYPE FUNCTION AD[4]/ RMODE0 I/O Data Bus D[4] or Address/Data Bus AD[4]/Receive Framing Mode Select Bi

DS26503 T1/E1/J1 BITS Element 19 of 123 NAME TYPE FUNCTION A6/MPS0 I Address Bus Bit A[6]/MCLK Prescale Select A6: In nonmultiplexed bus operation

DS26503 T1/E1/J1 BITS Element 2 of 123 TABLE OF CONTENTS 1. FEATURES...

DS26503 T1/E1/J1 BITS Element 20 of 123 NAME TYPE FUNCTION A0/E1TS I Address Bus Bit A[0]/E1 Termination Select A0: In nonmultiplexed bus operation

DS26503 T1/E1/J1 BITS Element 21 of 123 4.5 JTAG NAME TYPE FUNCTION JTCLK I JTAG Clock. This clock input is typically a low frequency (less than 10

DS26503 T1/E1/J1 BITS Element 22 of 123 4.7 Power NAME TYPE FUNCTION DVDD — Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD

DS26503 T1/E1/J1 BITS Element 23 of 123 5. PINOUT Table 5-1. LQFP Pinout MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 1 I/O AD2 SCL

DS26503 T1/E1/J1 BITS Element 24 of 123 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 17 I TCLK TCLK TCLK External Transmit Clock

DS26503 T1/E1/J1 BITS Element 25 of 123 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 60 I CS CS RLB Parallel Port Mode: Chip Select (

DS26503 T1/E1/J1 BITS Element 26 of 123 6. HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconf

DS26503 T1/E1/J1 BITS Element 27 of 123 6.3 Line Build-Out Table 6-3. E1 Line Build-Out L2 PIN 13 L1 PIN 12 L0 PIN 11 APPLICATION N (1) RETURN LOS

DS26503 T1/E1/J1 BITS Element 28 of 123 6.5 Transmitter Operating Modes Table 6-6.Transmit Path Operating Mode TMODE3 PIN 62 TMODE2 PIN 48 TMODE1 PI

DS26503 T1/E1/J1 BITS Element 29 of 123 Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 PIN 16 MPS0 PIN 15 JACKS PIN 46 MCLK (MHz) 0 0 0 2.048 0 0 1 Res

DS26503 T1/E1/J1 BITS Element 3 of 123 8. T1 FRAMER/FORMATTER CONTROL REGISTERS ...40 8.1 T1 CONT

DS26503 T1/E1/J1 BITS Element 30 of 123 7. PROCESSOR INTERFACE The DS26503 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[

DS26503 T1/E1/J1 BITS Element 31 of 123 are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining da

DS26503 T1/E1/J1 BITS Element 32 of 123 7.3 Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE REGISTER NAME REGISTER ABBREVIATION

DS26503 T1/E1/J1 BITS Element 33 of 123 ADDRESS TYPE REGISTER NAME REGISTER ABBREVIATION 43 R/W Transmit Si Non-Align Frame TSiNAF 44 R/W Tran

DS26503 T1/E1/J1 BITS Element 34 of 123 7.3.1 Power-Up Sequence The DS26503 contains an on-chip power-up reset function, which automatically clears

DS26503 T1/E1/J1 BITS Element 35 of 123 7.3.3 Mode Configuration Register Register Name: MCREG Register Description: Mode Configuration Register R

DS26503 T1/E1/J1 BITS Element 36 of 123 Bit 4-7/ Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path fo

DS26503 T1/E1/J1 BITS Element 37 of 123 Bit 3-4/Transmit PLL Input Frequency Select (TPLLIFS[1:0]). These bits are used to indicate the reference

DS26503 T1/E1/J1 BITS Element 38 of 123 7.4 Interrupt Handling Various alarms, conditions, and events in the DS26503 can cause interrupts. For simpl

DS26503 T1/E1/J1 BITS Element 39 of 123 7.6 Information Registers Information registers operate the same as status registers except they cannot caus

DS26503 T1/E1/J1 BITS Element 4 of 123 17. FUNCTIONAL TIMING DIAGRAMS ...

DS26503 T1/E1/J1 BITS Element 40 of 123 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26503 is configured via a set of fi

DS26503 T1/E1/J1 BITS Element 41 of 123 Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6

DS26503 T1/E1/J1 BITS Element 42 of 123 Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7

DS26503 T1/E1/J1 BITS Element 43 of 123 Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7

DS26503 T1/E1/J1 BITS Element 44 of 123 Register Name: T1CCR Register Description: T1 Common Control Register Register Address: 07h Bit # 7 6 5

DS26503 T1/E1/J1 BITS Element 45 of 123 Table 8-1. T1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (Note 1) Over a 3ms windo

DS26503 T1/E1/J1 BITS Element 46 of 123 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26503 is configured via a set of tw

DS26503 T1/E1/J1 BITS Element 47 of 123 Table 9-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. FAS

DS26503 T1/E1/J1 BITS Element 48 of 123 9.2 E1 Information Registers Register Name: INFO2 Register Description: Information Register 2 Register Ad

DS26503 T1/E1/J1 BITS Element 49 of 123 Table 9-2. E1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RLOF An RLOF condition exists on

DS26503 T1/E1/J1 BITS Element 5 of 123 LIST OF FIGURES Figure 3-1. Block Diagram ...

DS26503 T1/E1/J1 BITS Element 50 of 123 Register Name: SR2 Register Description: Status Register 2 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Na

DS26503 T1/E1/J1 BITS Element 51 of 123 Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 52 of 123 10. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1

DS26503 T1/E1/J1 BITS Element 53 of 123 Table 10-1. TS Pin Functions TRANSMIT MODE IOCR.3 IOCR.2 IOCR.1 TS FUNCTION T1/E1 0 0 0 Frame sync input

DS26503 T1/E1/J1 BITS Element 54 of 123 Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5

DS26503 T1/E1/J1 BITS Element 55 of 123 11. T1 SYNCHRONIZATION STATUS MESSAGE The DS26503 has a BOC controller to handle SSM services in T1 mode.

DS26503 T1/E1/J1 BITS Element 56 of 123 11.3 Receive BOC The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now opera

DS26503 T1/E1/J1 BITS Element 57 of 123 Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 5 4 3 2 1

DS26503 T1/E1/J1 BITS Element 58 of 123 Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1) Register Description: Receive FDL Register R

DS26503 T1/E1/J1 BITS Element 59 of 123 Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 5 4 3 2 1

DS26503 T1/E1/J1 BITS Element 6 of 123 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications...

DS26503 T1/E1/J1 BITS Element 60 of 123 Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 61 of 123 Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Na

DS26503 T1/E1/J1 BITS Element 62 of 123 Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 63 of 123 Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 5 4 3 2

DS26503 T1/E1/J1 BITS Element 64 of 123 12. E1 SYNCHRONIZATION STATUS MESSAGE The DS26503 provides access to both the transmit and receive Sa/Si b

DS26503 T1/E1/J1 BITS Element 65 of 123 Register Name: RSiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h Bit #

DS26503 T1/E1/J1 BITS Element 66 of 123 Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 6 5 4 3 2 1

DS26503 T1/E1/J1 BITS Element 67 of 123 Register Name: RSa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 5 4 3 2 1 0

DS26503 T1/E1/J1 BITS Element 68 of 123 Register Name: RSa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 5 4 3 2 1 0

DS26503 T1/E1/J1 BITS Element 69 of 123 Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h Bit #

DS26503 T1/E1/J1 BITS Element 7 of 123 1. FEATURES 1.1 General § 64-pin, 10mm x 10mm LQFP package § 3.3V supply with 5V-tolerant inputs and output

DS26503 T1/E1/J1 BITS Element 70 of 123 Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 5 4 3 2 1

DS26503 T1/E1/J1 BITS Element 71 of 123 Register Name: TSa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 5 4 3 2 1 0

DS26503 T1/E1/J1 BITS Element 72 of 123 Register Name: TSa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 5 4 3 2 1 0

DS26503 T1/E1/J1 BITS Element 73 of 123 Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bit # 7

DS26503 T1/E1/J1 BITS Element 74 of 123 12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will

DS26503 T1/E1/J1 BITS Element 75 of 123 Register Name: RNAF Register Description: Receive Non-Align Frame Register Register Address: 57h Bit # 7

DS26503 T1/E1/J1 BITS Element 76 of 123 Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bit # 7

DS26503 T1/E1/J1 BITS Element 77 of 123 13. LINE INTERFACE UNIT (LIU) The LIU in the DS26503 contains three sections: the receiver, which handles c

DS26503 T1/E1/J1 BITS Element 78 of 123 13.1 LIU Operation The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 li

DS26503 T1/E1/J1 BITS Element 79 of 123 13.2.2 Receive G.703 Section 10 Synchronization Signal The DS26503 can receive a 2.048MHz square-wave synch

DS26503 T1/E1/J1 BITS Element 8 of 123 1.4 Framer/Formatter § Full receive and transmit path transparency § T1 framing formats include D4 and ESF

DS26503 T1/E1/J1 BITS Element 80 of 123 The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, t

DS26503 T1/E1/J1 BITS Element 81 of 123 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15

DS26503 T1/E1/J1 BITS Element 82 of 123 13.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Add

DS26503 T1/E1/J1 BITS Element 83 of 123 T1 Mode L2 L1 L0 APPLICATION N (1) RETURN LOSS Rt (1) 0 0 0 DSX-1 (0 to 133 feet)/0dB CSU 1:2 N.M

DS26503 T1/E1/J1 BITS Element 84 of 123 Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 31h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 85 of 123 Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 5 4 3 2

DS26503 T1/E1/J1 BITS Element 86 of 123 Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 87 of 123 Register Name: INFO1 Register Description: Information Register 1 Register Address: 11h Bit # 7 6 5 4 3 2

DS26503 T1/E1/J1 BITS Element 88 of 123 Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 5 4 3 2 1 0 Na

DS26503 T1/E1/J1 BITS Element 89 of 123 Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 9 of 123 2. SPECIFICATIONS COMPLIANCE The DS26503 meets all applicable sections of the relevant latest telecommunicati

DS26503 T1/E1/J1 BITS Element 90 of 123 13.8 Recommended Circuits Figure 13-4. Basic Interface TTIP TRING RTIP RRIN

DS26503 T1/E1/J1 BITS Element 91 of 123 Figure 13-5. Protected Interface Using Internal Receive Termination TTIP

DS26503 T1/E1/J1 BITS Element 92 of 123 13.9 Component Specifications Table 13-1. Transformer Specifications SPECIFICATION RECOMMENDED VALUE Turns

DS26503 T1/E1/J1 BITS Element 93 of 123 Figure 13-6. E1 Transmit Pulse Template Figure 13-7. T1 Transmit Pulse Template 0-0.1-

DS26503 T1/E1/J1 BITS Element 94 of 123 Figure 13-8. Jitter Tolerance (T1 Mode) Figure 13-9. Jitter Tolerance (E1 Mode) UNIT

DS26503 T1/E1/J1 BITS Element 95 of 123 Figure 13-10. Jitter Attenuation (T1 Mode) Figure 13-11. Jitter Attenuation (E1 Mod

DS26503 T1/E1/J1 BITS Element 96 of 123 14. LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Ad

DS26503 T1/E1/J1 BITS Element 97 of 123 15. 6312kHz SYNCHRONIZATION INTERFACE The DS26503 has a 6312kHz Synchronization Interface mode of operation

DS26503 T1/E1/J1 BITS Element 98 of 123 16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26503 supports the standard IEEE 1149.1 inst

DS26503 T1/E1/J1 BITS Element 99 of 123 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level a