
FeaturesApplicationsCMOS RESET ICBD48XXG/FVEBD49XXG/FVE Selection guideRohm's BD48XXG/FVE and BD49XXG/FVE are series of high-accuracy, low
Characteristic data (Reference data)521 43 1076 980.51.01.5VDD [V]IDD [ A]0[BD4842G/FVE]1.5 2 2.51015180.5 150VDS [V]IOL [mA]VDD=1.2VVDD=2.4V[
VDDVDDVOUTGNDA Fig.34Circuit current on ON (VS-0.2V)Ta [°C]20-20 0 10040 80600.51.0IDD [ A]-40 [BD4842G/FVE]100RL=470K VDDVVDD
Taping specificationRectangular recess to hold a componentCircular feed holeBAD1P2P0WFED0P1tKPackage SSOP5 (SMP5C2)SymbolDimensionSymbolDimensi
3)Standard packaged quantity and IC direction The standard packaged quantity is 3,000 pcs/reel. Orders should be in multiples of the standard package
(UNIT:mm)SSOP5(SMP5C2)(5)2.9±0.24° + 6°-4°1.6-0.1+0.22.8±0.2(3)(4)(2)(1)+0.050.13–0.030.2MIN0.950.11.25MAX0.05±0.051.1±0.050.42+0.05-0.04VSOF5(EMP5
Reference land pattern Part number and marking of samplesFor actual designing, take the board density, mountability, dimension tolerance, etc.
Appendix Appendix1-Rev1.1 The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as a
Line-up Pin layoutNch Open drain output ( BD48XXG/FVE ) CMOS output ( BD49XXG/FVE )Detection voltage VS ( V ) Ta=25°CDetection voltage
To prevent the functional deterioration or thermal damage of semiconductor devices and ensure their service life and reliability, they must be designe
Power dissipationWhen it is used in the ambient temperature of (Ta)=25°C and more, make reference to each thermal derating characteristics of used
Operating explanationWhen VDD is equal to or more than the release voltage (Vs+ Vs), output VOUT is in "H" mode. (Nch output transisto
Application circuit1)Application circuit as ordinal supply detection reset is shown below.Output type of BD48XXG/FVE series (Open drain type) and
• Test dataFig.15 BD4845G TPLH output waveformFig.16 BD4845G TPHL output waveformFig.17 BD4945G TPLH output waveformFig.18 BD4945G TPHL output wave
Hysteresis > R X { (Circuit current at ON) - (Circuit current at OFF) }3)Application circuit when it is used as Power-on reset is shown below. (
Establishment of RESET transfer delay time • Delay time at the rise of VDD TPLH : Time until when VOUT is 1/2 of VDD after the rise of VDD, and b
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