Rainbow-electronics DS1558Y Uživatelský manuál stáhnout pdf (Strana 5)

DS1558

5 of 18

Table 1. OPERATING MODES

CE OE WE

DQ0–DQ7 MODE POWER

X X High-Z Deselect Standby

Write Active

OUT

Read Active

> V

High-Z Read Active

< V

X X X High-Z Deselect CMOS Standby

< V

X X X High-Z Data Retention Battery Current

DATA READ MODE

The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows

ripple-through access to any valid address location. Valid data is available at the DQ pins within t

after

the last address input is stable, provided that

CE and OE access times are satisfied. If CE or OE access

times are not met, valid data is available at the latter of chip-enable access (t

CEA

) or at output-enable

access time (t

OEA

). The state of the data input/output pins (DQ) is controlled by CE and OE . If the

outputs are activated before t

, the data lines are driven to an intermediate state until t

. If the address

inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time

(tOH), but then goes indeterminate until the next address access.

DATA WRITE MODE

The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle. CE and WE must return inactive for a minimum of t

prior to the initiation of a subsequent

read or write cycle. Data in must be valid t

prior to the end of the write and remain valid for t

afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE

transitioning low, the data bus can become active with read data defined by the address inputs. A low

transition on WE then disables the outputs t

WEZ

after WE goes active.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written and read only when V

is greater than V

However, when V

is below the power-fail point V

(point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. When V

falls below the battery switch

point V

(battery supply level), device power is switched from the V

pin to the backup battery. RTC

operation and SRAM data are maintained from the battery until V

is returned to nominal levels.

The 3.3V device is fully accessible and data can be written and read only when V

is greater than V

When V

falls below V

, access to the device is inhibited. If V

is less than V

, the device power is

switched from V

to the internal backup lithium battery when V

drops below V

. If V

is greater

than V

, the device power is switched from V

to the internal backup lithium battery when V

drops

below V

. RTC operation and SRAM data are maintained from the battery until V

is returned to

nominal levels.

All control, data, and address signals must be powered down when V

is powered down.

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