Rainbow-electronics DS4266 Uživatelský manuál stáhnout pdf (Strana 3)

DS4266

DDR Clock Oscillator

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

= 3.135V to 3.465V, T

= -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LVDS

Output High Voltage V

OHLVDSO

100 differential load (Note 1) 1.475 V

Output Low Voltage V

OLLVDSO

100 differential load (Note 1) 0.925 V

Differential Output Voltage

ODLVDSO

100 differential load 250 425 mV

Output Common-Mode Voltage

Variation

LVDSOCOM

100 differential load 150 mV

Change in Differential Magnitude

or Complementary Inputs



ODLVDSO

100 differential load 25 mV

Offset Output Voltage V

OFFLVDSO

100 differential load (Note 1) 1.125 1.275 V

Differential Output Impedance R

OLVDSO

80 140 

VSSLVDSO

OUTN or OUTP shorted to ground and

measure the current in the shorting path

Output Current

LVDSO

OUTN or OUTP shorted together 6.5

Output Rise Time (Differential) t

RLVDSO

20% to 80% 175 ps

Output Fall Time (Differential) t

FLVDSO

80% to 20% 175 ps

Duty Cycle D

CYCLE_LVDS

48 52 %

Propagation Delay from OE Going

Low to Logical 1 at OUTP

PA1

200 ns

Propagation Delay from OE Going

High to Output Active

P1A

200 ns

LVPECL

Output High Voltage V

Output connected to 50 at PECL_BIAS

at V

- 2.0V

1.085

0.88

Output Low Voltage V

Output connected to 50 at PECL_BIAS

at V

- 2.0V

1.825

1.62

Differential Voltage V

DIFF_PECL

Output connected to 50 at PECL_BIAS

at V

- 2.0V

0.595 0.710 V

Rise Time t

R-PECL

200 ps

Fall Time t

F-PECL

200 ps

Duty Cycle D

CYCLE_PECL

48 52 %

Propagation Delay from OE Going

Low to Output High Impedance

PAZ

200 ns

Propagation Delay from OE Going

High to Output Active

PZA

200 ns

Note 1: All voltages referenced to ground.

Note 2: AC parameters are guaranteed by design and not production tested.

Note 3: Frequency stability is calculated as: Δf

TOTAL

= Δf

TEMP

+ Δf

VCC

x (3.3 x 5%) + Δf

LOAD

+ Δf

AGING

1 2 3 4 5 6

DDR Clock Oscillator 1

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