
Description of Boundary-Scan
Circuitry
The SCAN92LV090 features two unique Scan test modes,
each which requires a unique BSDL model depending on the
level of test access and fault coverage goals. In the first
mode (Mode0), only the TTL Inputs and Outputs of each
transceiver are accessible via a 1149.1 compliant protocol.
In the second mode (Mode1), the TTL Inputs and Outputs
are accessible by a 1149.1 compliant method while the
Differential I/O pins are accessible by a 1149.1 compatible
technique which evaluates the signal integrity and modifies
the data in the differential BSR as appropriate.
All test modes are handled by the ATPG software, and BSDL
selection should be invisible to the user.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
10124209
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
Instruction Register Scan Chain Definition
10124210
MSB
→
LSB (Mode0)
Instruction Code Instruction
00000000 EXTEST
10000010 SAMPLE/PRELOAD
10000111 CLAMP
00000110 HIGHZ
All Others BYPASS
MSB
→
LSB (Mode1)
Instruction Code Instruction
10011001 EXTEST
10010010 SAMPLE/PRELOAD
10001111 CLAMP
00000110 HIGHZ
All Others BYPASS
10124220
Mode 0 Boundary Scan Register Configuration
10124221
Mode 1 Boundary Scan Register Configuration
SCAN92LV090
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