
58
ATtiny2313
2543A–AVR–08/03
• T0 – Port D, Bit 4
CKOUT: System Clock Output
T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits
CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0).
• INT1 – Port D, Bit 3
INT0: External Interrupt Source 0. The PD3 pin can serve as an external interrupt
source to the MCU.
• INT0/XCK/CKOUT – Port D, Bit 2
INT1: External Interrupt Source 1. The PD2 pin can serve as en axternal interrupt
source to the MCU.
XCK: USART Transfer Clock used only by Synchronous Transfer mode.
CKOUT: System Clock Output
• TXD – Port D, Bit 1
TXD: UART Data Transmitter.
• RXD – Port D, Bit 0
RXD: UART Data Receiver.
Table 30 and Table 31 relates the alternate functions of Port D to the overriding signals
shown in Figure 25 on page 52.
Table 30. Overriding Signals for Alternate Functions PD7..PD4
Signal
Name PD6/ICP PD5/OC1B/T1 PD4/T0
PUOE000
PUOV000
DDOE 0 0 0
DDOV 0 0 0
PVOE 0 OC1B_PVOE 0
PVOV 0 OC1B_PVOV 0
PTOE000
DIEOE ICP ENABLE T1 ENABLE T0 ENABLE
DIEOV111
DI ICP INPUT T1 INPUT T0 INPUT
AIO––AIN1
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