Rainbow-electronics T89C51AC2 Uživatelský manuál stáhnout pdf (Strana 82)

T89C51AC2

Rev. B – 19-Dec-01

16.3 ADC Converter

Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set (see Figure 39). Clear this flag for re-

arming the interrupt.

ThebitsSCH0toSCH2inADCONregisterareusedfortheanaloginputchannel

selection.

Table 43. Selected Analog input

16.4 Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (see section

“AC-DC”)

16.5 Clock Selection The ADC clock is the same as CPU.

The maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to

generate the ADC clock from the oscillator frequency.

Figure 38. A/D Converter clock

SCH2 SCH1 SCH0 Selected Analog input

000AN0

001AN1

010AN2

011AN3

100AN4

101AN5

110AN6

111AN7

Prescaler ADCLK

A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 109 110

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Rainbow-electronics T89C51AC2 Uživatelský manuál Strana 82