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TL/H/12441
ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital Converter
December 1995
ADC12041
12-Bit Plus Sign 216 kHz Sampling
Analog-to-Digital Converter
General Description
Operating from a single 5V power supply the ADC12041 is a
12 bit
a
sign, parallel I/O, self-calibrating, sampling analog-
to-digital converter (ADC). The maximum sampling rate is
216 kHz. On request, the ADC goes through a self-calibra-
tion process that adjusts linearity, zero and full-scale errors.
The ADC12041 can be configured to work with many popu-
lar microprocessors/microcontrollers including National’s
HPC family, Intel386 and 8051, TMS320C25, Motorola
MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Key Specifications (f
CLK
e
12 MHz)
Y
Resolution 12-bits
a
sign
Y
13-bit conversion time 3.6 ms, max
Y
13-bit throughput rate 216 ksamples/s, min
Y
Integral Linearity Error (ILE)
g
1 LSB, max
Y
Single supply
a
5V
g
10%
Y
V
IN
range GND to V
A
a
Y
Power consumption:
Normal operation 33 mW, max
Stand-by mode 75 mw, max
Features
Y
Fully differential analog input
Y
Programmable acquisition times and user-controllable
throughput rates
Y
Programmable data bus width (8/13 bits)
Y
Built-in Sample-and-Hold
Y
Programmable auto-calibration and auto-zero cycles
Y
Low power standby mode
Y
No missing codes
Applications
Y
Medical instrumentation
Y
Process control systems
Y
Test equipment
Y
Data logging
Y
Inertial guidance
Block Diagram
TL/H/124411
TRI-STATE
É
is a registered trademark of National Semiconductor Corporations.
C
1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.
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Shrnutí obsahu

Strany 1 - Analog-to-Digital Converter

TL/H/12441ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital ConverterDecember 1995ADC1204112-Bit Plus Sign 216 kHz SamplingAnalog-to-Digita

Strany 2 - Ordering Information

Electrical Characteristics (Continued)TL/H/12441–9FIGURE 5a. Transfer CharacteristicTL/H/12441–10FIGURE 5b. Simplified Error vs Output Code without Au

Strany 3 - Absolute Maximum Ratings

Electrical Characteristics (Continued)TL/H/12441–11FIGURE 5c. Simplified Error vs Output Code after Auto-Calibration CycleTL/H/12441–12FIGURE 6. Offse

Strany 4

Timing DiagramsTL/H/12441–13FIGURE 7a. Sync-Out Write (WMODEe1, BWe1), Read and Convert CyclesTL/H/12441–14FIGURE 7b. Sync-In Write (WMODEe1, BWe1), R

Strany 5

Timing Diagrams (Continued)TL/H/12441–46FIGURE 7c. Sync-Out Write (WMODEe0, BWe1), Read and Convert CyclesTL/H/12441–47FIGURE 7d. Sync-In Write (WMODE

Strany 6 - Notes on Specifications

Timing Diagrams (Continued)TL/H/12441–48FIGURE 7e. Sync-Out Read and Convert CyclesTL/H/12441–49FIGURE 7f. Sync-In Read and Convert Cycles14

Strany 7 - Figure 6

Timing Diagrams (Continued)TL/H/12441–50FIGURE 7g. 8-bit Bus Read Cycle (Sync-Out)TL/H/12441–51FIGURE 7h. 8-bit Bus Read Cycle (Sync-In)15

Strany 8 - Electrical Characteristics

Timing Diagrams (Continued)TL/H/12441–15FIGURE 7i. Write Signal Negates RDY (Writing the Standby, Auto-Cal or Auto-Zero Command)TL/H/12441–16FIGURE 7j

Strany 9 - TL/H/12441–8

Typical Performance Characteristics (See Note 19, Electrical Characteristic Section)Change vs Clock FrequencyIntegral Linearity Error (INL)TL/H/12441–

Strany 10 - (Continued)

Typical Performance Characteristics (See Note 21, Electrical Characteristic Section) (Continued)Clock FrequencySupply Current vsTL/H/12441–29Clock Fre

Strany 11

Typical Performance Characteristics (Continued) The curves were obtained under the following condi-tions. RSe50X,TAe25§C, VAaeVDae5V, VREFe4.096V, fCL

Strany 12 - Timing Diagrams

Connection Diagrams28-Pin SSOPTL/H/12441–2Order Number ADC12041CIMSASee NS Package Number MSA2828-Pin PLCCTL/H/12441–3Order Number ADC12041CIVSee NS P

Strany 13 - Timing Diagrams (Continued)

Pin DescriptionPLCC andPinSSOP Pkg.NameDescriptionPin Number5VINaThe analog ADC inputs. VINais the non-inverting (positive) input and VINbis the inver

Strany 14

Register Bit DescriptionCONFIGURATION REGISTER (Write Only)This is an 8-bit write-only register that is used to program the functionality of the ADC12

Strany 15

Functional DescriptionThe ADC12041 is programmed through a digital interfacethat supports an 8-bit or 16-bit data bus. The digital inter-face consists

Strany 16

Features and Operating Modes (Continued)If the settling time of the source is greater than 500 ns, theacquisition time should be about 300 ns longer t

Strany 17

Features and Operating Modes (Continued)SYNC-IN/SynchronousFor the SYNC-IN case, it is assumed that a series of SYNCpulses at the desired sampling rat

Strany 18 - TL/H/12441–32

Analog Application InformationREFERENCE VOLTAGEThe ADC12041 has two reference inputs, VREFaandVREFb. They define the zero to full-scale range of the a

Strany 19

Analog Application Information (Continued)INPUT CURRENTAt the start of the acquisition window (tAcqSYNOUT) a charg-ing current (due to capacitive swit

Strany 20 - Pin Description

Analog Application Information (Continued)TL/H/12441–45FIGURE 10. Top View of Printed Circuit Board for a 28-Pin PLCC ADC12041When measuring AC input

Strany 22 - Features and Operating Modes

Physical Dimensions inches (millimeters)28-Lead Molded Plastic Leaded Chip CarrierOrder Number ADC12041CIVNS Package Number V28A29

Strany 23 - SYNC-OUT/Asynchronous

Absolute Maximum Ratings(Notes 1 and 2)Supply Voltage (VAaand VDa) 6.0VVoltage at all Inputsb0.3V to Vaa0.3VlVAabVDal300 mVlAGNDbDGNDl300 mVInput Curr

Strany 24 - SYNC-IN/Synchronous

ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital ConverterPhysical Dimensions inches (millimeters) (Continued)28-Lead SSOPOrder Number ADC

Strany 25 - Figure 9

Power Supply Characteristics The following specifications apply to the ADC12041 for VAaeVDae5V,VREFae4.096V, VREFbe0.0V, 12-bitasign conversion mode,

Strany 26 - Figure 10

Digital Logic Input/Output Characteristics The following specifications apply to the ADC12041 forVAaeVDae5V, VREFae4.096V, VREFbe0.0V, 12-bitasign con

Strany 27

Digital Timing Characteristics The following specifications apply to the ADC12041, 13-bit data bus width,VAaeVDae5V, fCLKe12 MHz, tfe3 ns and CLe50 pF

Strany 28

Notes on Specifications (Continued)Note 6: Each input is protected by a nominal 6.5V breakdown voltage zener diode to GND, as shown below, input volta

Strany 29 - NS Package Number V28A

Electrical CharacteristicsTL/H/12441–5FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)TL/H/12441–6FIGURE 2. Output Di

Strany 30

Electrical Characteristics (Continued)TL/H/12441–7FIGURE 3. VREFOperating Range (General Case)TL/H/12441–8FIGURE 4. VREFOperating Range for VAe5V9

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