Rainbow-electronics AT89C51SND1C Uživatelský manuál stáhnout pdf (Strana 14)

AT8xC51SND1C

4109E–8051–06/03

Figure 9. PLL Filter Connection

PLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as clock generation

is enabled, the user must wait until the lock indicator is set to ensure the clock output is

stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface

clock frequencies.

Figure 10. PLL Programming Flow

VSS

FILT

VSS

PLL

Programming

Configure Dividers

N6:0 = xxxxxxb

R9:0 = xxxxxxxxxxb

Enable PLL

PLLRES = 0

PLLEN = 1

PLL Locked?

PLOCK = 1?

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 209 210

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Rainbow-electronics AT89C51SND1C Uživatelský manuál Strana 14