Rainbow-electronics ATmega161L Uživatelský manuál stáhnout pdf (Strana 32)

ATmega161(L)

1228C–AVR–08/02

• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at

Vector $010) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the

OCF1B bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 4

– TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at Vector

$00a) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set

in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 3

– TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt

(at Vector $00C) is executed if a capture-triggering event occurs on pin 31, ICP, i.e.,

when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 2

– OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at

Vector $008) is executed if a Compare2 match in Timer/Counter2 occurs, i.e., when the

OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 1

– TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at Vector

$016) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set

in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 0

– OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at

Vector $014) is executed if a Compare 0 Match in Timer/Counter0 occurs, i.e., when the

OCF0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

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Rainbow-electronics ATmega161L Uživatelský manuál Strana 32