Rainbow-electronics ATmega162V Uživatelský manuál

2513E–AVR–09/03Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 131 Powerful Instructions – Most Single-

10ATmega162/V2513E–AVR–09/03General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve

100ATmega162/V2513E–AVR–09/03When OC0 is connected to the pin, the function of the COM01:0 bits depends on theWGM01:0 bit setting. Table 48 shows the

101ATmega162/V2513E–AVR–09/03• Bit 2:0 – CS02:0: Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter.If ex

102ATmega162/V2513E–AVR–09/03• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt EnableWhen the OCIE0 bit is written to one, and the I-bit

103ATmega162/V2513E–AVR–09/03Timer/Counter0, Timer/Counter1, and Timer/Counter3 PrescalersTimer/Counter3, Timer/Counter1, and Timer/Counter0 share the

104ATmega162/V2513E–AVR–09/03Each half period of the external clock applied must be longer than one system clockcycle to ensure correct sampling. The

105ATmega162/V2513E–AVR–09/0316-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)The 16-bit Timer/Counter unit allows accurate program execution t

106ATmega162/V2513E–AVR–09/03Figure 46. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 32 on page 71, and Table 38

107ATmega162/V2513E–AVR–09/03(OCnA/B). See “Output Compare Units” on page 114. The Compare Match event willalso set the Compare Match Flag (OCFnA/B) w

108ATmega162/V2513E–AVR–09/03Accessing 16-bit RegistersThe TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVRCPU via the 8-

109ATmega162/V2513E–AVR–09/03Therefore, when both the main code and the interrupt code update the temporary regis-ter, the main code must disable the

11ATmega162/V2513E–AVR–09/03The X-register, Y-register, and Z-registerThe registers R26..R31 have some added functions to their general purpose usage.

110ATmega162/V2513E–AVR–09/03The following code examples show how to do an atomic write of the TCNTn Registercontents. Writing any of the OCRnA/B or I

111ATmega162/V2513E–AVR–09/03Timer/Counter Clock SourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clocksource i

112ATmega162/V2513E–AVR–09/03how waveforms are generated on the Output Compare outputs OCnx. For more detailsabout advanced counting sequences and wav

113ATmega162/V2513E–AVR–09/03Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading thelow byte (ICRnL) and then the h

114ATmega162/V2513E–AVR–09/03(ICFn) must be cleared by software (writing a logical one to the I/O bit location). Formeasuring frequency only, the clea

115ATmega162/V2513E–AVR–09/03sequence. The synchronization prevents the occurrence of odd-length, non-symmetricalPWM pulses, thereby making the output

116ATmega162/V2513E–AVR–09/03Compare Match Output UnitThe Compare Output mode (COMnx1:0) bits have two functions. The waveform genera-tor uses the COM

117ATmega162/V2513E–AVR–09/03Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and

118ATmega162/V2513E–AVR–09/03Figure 51. CTC Mode, Timing DiagramAn interrupt can be generated at each time the counter value reaches the TOP value by

119ATmega162/V2513E–AVR–09/03Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) pro-vides a high frequency PWM

12ATmega162/V2513E–AVR–09/03Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. TheAVR CP

120ATmega162/V2513E–AVR–09/03When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the c

121ATmega162/V2513E–AVR–09/03Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1,2, 3, 10, or 11) p

122ATmega162/V2513E–AVR–09/03ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers areupdated with the double buffer value

123ATmega162/V2513E–AVR–09/03pared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are p

124ATmega162/V2513E–AVR–09/03than any of the compare registers, a Compare Match will never occur between theTCNTn and the OCRnx.As Figure 54 shows the

125ATmega162/V2513E–AVR–09/03Timer/Counter Timing DiagramsThe Timer/Counter is a synchronous design and the timer clock (clkTn) is thereforeshown as a

126ATmega162/V2513E–AVR–09/03Figure 57. Timer/Counter Timing Diagram, no PrescalingFigure 58 shows the same timing data, but with the prescaler enabl

127ATmega162/V2513E–AVR–09/0316-bit Timer/Counter Register DescriptionTimer/Counter1 Control Register A – TCCR1ATimer/Counter3 Control Register A – TC

128ATmega162/V2513E–AVR–09/03Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thefast PWM mode.Note: 1. A special case o

129ATmega162/V2513E–AVR–09/03• Bit 1:0 – WGMn1:0: Waveform Generation ModeCombined with the WGMn3:2 bits found in the TCCRnB Register, these bits cont

13ATmega162/V2513E–AVR–09/03also be moved to the start of the Boot Flash section by programming the BOOTRSTFuse, see “Boot Loader Support – Read-While

130ATmega162/V2513E–AVR–09/03Timer/Counter1 Control Register B – TCCR1BTimer/Counter3 Control Register B – TCCR3B• Bit 7 – ICNCn: Input Capture Noise

131ATmega162/V2513E–AVR–09/03• Bit 2:0 – CSn2:0: Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter, seeF

132ATmega162/V2513E–AVR–09/03Timer/Counter1 – TCNT1H and TCNT1LTimer/Counter3 – TCNT3H and TCNT3LThe two Timer/Counter I/O locations (TCNTnH and TCNTn

133ATmega162/V2513E–AVR–09/03The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNTn). A match

134ATmega162/V2513E–AVR–09/03• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt EnableWhen this bit is written to one, and the I-flag

135ATmega162/V2513E–AVR–09/03Timer/Counter Interrupt Flag Register – TIFR(1)Note: 1. This register contains flag bits for several Timer/Counters, but

136ATmega162/V2513E–AVR–09/03Extended Timer/Counter Interrupt Flag Register – ETIFR(1)Note: 1. This register contains flag bits for several Timer/Coun

137ATmega162/V2513E–AVR–09/038-bit Timer/Counter2 with PWM and Asynchronous operationTimer/Counter2 is a general purpose, single channel, 8-bit Timer/

138ATmega162/V2513E–AVR–09/03The Timer/Counter can be clocked internally, via the prescaler, or asynchronouslyclocked from the TOSC1/2 pins, as detail

139ATmega162/V2513E–AVR–09/03Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 60 shows a b

14ATmega162/V2513E–AVR–09/03When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending inte

140ATmega162/V2513E–AVR–09/03Figure 61. Output Compare Unit, Block DiagramThe OCR2 Register is double buffered when using any of the Pulse Width Modu

141ATmega162/V2513E–AVR–09/03resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 valueequal to BOTTOM when the counter is do

142ATmega162/V2513E–AVR–09/03The design of the Output Compare pin logic allows initialization of the OC2 state beforethe output is enabled. Note that

143ATmega162/V2513E–AVR–09/03Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used tom

144ATmega162/V2513E–AVR–09/03Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high fre-quency PWM waveform gene

145ATmega162/V2513E–AVR–09/03The PWM frequency for the output can be calculated by the following equation:The N variable represents the prescale facto

146ATmega162/V2513E–AVR–09/03The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-TOM. The Interrupt Flag can be used to ge

147ATmega162/V2513E–AVR–09/03Figure 66. Timer/Counter Timing Diagram, no PrescalingFigure 67 shows the same timing data, but with the prescaler enabl

148ATmega162/V2513E–AVR–09/03Figure 69. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, withPrescaler (fclk_I/O/8)8-bit Timer/Counte

149ATmega162/V2513E–AVR–09/03match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table60 and “Modes of Operation” on page 142.N

15ATmega162/V2513E–AVR–09/03AVR ATmega162 MemoriesThis section describes the different memories in the ATmega162. The AVR architecturehas two main mem

150ATmega162/V2513E–AVR–09/03• Bit 5:4 – COM21:0: Compare Match Output ModeThese bits control the Output Compare pin (OC2) behavior. If one or both of

151ATmega162/V2513E–AVR–09/03• Bit 2:0 – CS22:0: Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter, seeT

152ATmega162/V2513E–AVR–09/03Asynchronous operation of the Timer/CounterAsynchronous Status Register – ASSR• Bit 3 – AS2: Asynchronous Timer/Counter2W

153ATmega162/V2513E–AVR–09/03Asynchronous Operation of Timer/Counter2When Timer/Counter2 operates asynchronously, some considerations must be taken.•

154ATmega162/V2513E–AVR–09/03down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock si

155ATmega162/V2513E–AVR–09/03Timer/Counter Interrupt Flag Register – TIFR• Bit 4 – OCF2: Output Compare Flag 2The OCF2 bit is set (one) when a Compare

156ATmega162/V2513E–AVR–09/03Timer/Counter Prescaler Figure 70. Prescaler for Timer/Counter2The clock source for Timer/Counter2 is named clkT2S. clkT

157ATmega162/V2513E–AVR–09/03Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween

158ATmega162/V2513E–AVR–09/03When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user softw

159ATmega162/V2513E–AVR–09/03The following code examples show how to initialize the SPI as a Master and how to per-form a simple transmission. DDR_SPI

16ATmega162/V2513E–AVR–09/03SRAM Data Memory Figure 9 shows how the ATmega162 SRAM Memory is organized. Memory configura-tion B refers to the ATmega16

160ATmega162/V2513E–AVR–09/03The following code examples show how to initialize the SPI as a slave and how to per-form a simple reception.Note: 1. The

161ATmega162/V2513E–AVR–09/03SS Pin FunctionalitySlave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. WhenSS i

162ATmega162/V2513E–AVR–09/03• Bit 4 – MSTR: Master/Slave SelectThis bit selects Master SPI mode when written to one, and Slave SPI mode when writtenl

163ATmega162/V2513E–AVR–09/03SPI Status Register – SPSR• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF Flag is set. An

164ATmega162/V2513E–AVR–09/03Data Modes There are four combinations of SCK phase and polarity with respect to serial data,which are determined by cont

165ATmega162/V2513E–AVR–09/03USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial commu

166ATmega162/V2513E–AVR–09/03Figure 75. USART Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 34 on page 73, Table 39 on page 79, and Tab

167ATmega162/V2513E–AVR–09/03AVR USART vs. AVR UART – CompatibilityThe USART is fully compatible with the AVR UART regarding:• Bit locations inside al

168ATmega162/V2513E–AVR–09/03Signal description:txclk Transmitter clock. (Internal Signal)rxclk Receiver base clock. (Internal Signal)xcki Input from

169ATmega162/V2513E–AVR–09/03Double Speed Operation (U2X)The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit onlyhas ef

17ATmega162/V2513E–AVR–09/03When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y,

170ATmega162/V2513E–AVR–09/03Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (startand stop bits),

171ATmega162/V2513E–AVR–09/03If used, the parity bit is located between the last data bit and first stop bit of a serialframe.USART Initialization The

172ATmega162/V2513E–AVR–09/03Baud and Control Registers, and for these types of applications the initialization codecan be placed directly in the main

173ATmega162/V2513E–AVR–09/03Sending Frames with 9 Data BitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUC

174ATmega162/V2513E–AVR–09/03Empty Interrupt, otherwise a new interrupt will occur once the interrupt routineterminates.The Transmit Complete (TXC) Fl

175ATmega162/V2513E–AVR–09/03Receiving Frames with 5 to 8 Data BitsThe Receiver starts data reception when it detects a valid start bit. Each bit that

176ATmega162/V2513E–AVR–09/03Receiving Frames with 9 Data BitsIf 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCS

177ATmega162/V2513E–AVR–09/03The receive function example reads all the I/O Registers into the Register File beforeany computation is done. This gives

178ATmega162/V2513E–AVR–09/03Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Typeof parity check to be

179ATmega162/V2513E–AVR–09/03(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line isidle (i.e., no communication activity).

18ATmega162/V2513E–AVR–09/03EEPROM Data Memory The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a sep-arate data space, in w

180ATmega162/V2513E–AVR–09/03Figure 81. Stop Bit Sampling and Next Start Bit SamplingThe same majority voting is done to the stop bit as done for the

181ATmega162/V2513E–AVR–09/03The recommendations of the maximum receiver baud rate error was made under theassumption that the Receiver and Transmitte

182ATmega162/V2513E–AVR–09/03The Multi-processor Communication mode enables several slave MCUs to receive datafrom a Master MCU. This is done by first

183ATmega162/V2513E–AVR–09/03Accessing UBRRH/UCSRC RegistersThe UBRRH Register shares the same I/O location as the UCSRC Register. Thereforesome speci

184ATmega162/V2513E–AVR–09/03Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera-tion. However, in most applica

185ATmega162/V2513E–AVR–09/03USART Register DescriptionUSART I/O Data Register – UDRThe USART Transmit Data Buffer Register and USART Receive Data Buf

186ATmega162/V2513E–AVR–09/03UDRE is set after a Reset to indicate that the transmitter is ready.• Bit 4 – FE: Frame ErrorThis bit is set if the next

187ATmega162/V2513E–AVR–09/03• Bit 5 – UDRIE: USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDRE Flag. A

188ATmega162/V2513E–AVR–09/03USART Control and Status Register C – UCSRC(1)Note: 1. The UCSRC Register shares the same I/O location as the UBRRH Regis

189ATmega162/V2513E–AVR–09/03• Bit 2:1 – UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Cha

19ATmega162/V2513E–AVR–09/03The EEPROM Data Register – EEDR• Bits 7..0 – EEDR7.0: EEPROM DataFor the EEPROM write operation, the EEDR Register contain

190ATmega162/V2513E–AVR–09/03• Bit 11:0 – UBRR11:0: USART Baud Rate RegisterThis is a 12-bit register which contains the USART baud rate. The UBRRH co

191ATmega162/V2513E–AVR–09/03Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 3.6864 MHz

192ATmega162/V2513E–AVR–09/03Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 8.0000 MHz

193ATmega162/V2513E–AVR–09/03Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 16.0000 MH

194ATmega162/V2513E–AVR–09/03Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When t

195ATmega162/V2513E–AVR–09/03the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-ing the corresponding interrupt

196ATmega162/V2513E–AVR–09/03JTAG Interface and On-chip Debug SystemFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities

197ATmega162/V2513E–AVR–09/03The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN fuse

198ATmega162/V2513E–AVR–09/03Figure 84. TAP Controller State DiagramTest-Logic-ResetRun-Test/IdleShift-DRExit1-DRPause-DRExit2-DRUpdate-DRSelect-IR S

199ATmega162/V2513E–AVR–09/03TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of theBoundary-scan circ

2ATmega162/V2513E–AVR–09/03Pin Configurations Figure 1. Pinout ATmega162Disclaimer Typical values contained in this datasheet are based on simulation

20ATmega162/V2513E–AVR–09/03can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” onpage 216 for details about boot programmin

200ATmega162/V2513E–AVR–09/03Using the On-chip Debug systemAs shown in Figure 83, the hardware support for On-chip Debugging consists mainly of• A sca

201ATmega162/V2513E–AVR–09/03On-chip debug specific JTAG instructionsThe On-chip debug support is considered being private JTAG instructions, and dist

202ATmega162/V2513E–AVR–09/03Bibliography For more information about general Boundary-scan, the following literature can beconsulted:• IEEE: IEEE Std.

203ATmega162/V2513E–AVR–09/03IEEE 1149.1 (JTAG) Boundary-scanFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities Accord

204ATmega162/V2513E–AVR–09/03Data Registers The data registers relevant for Boundary-scan operations are:• Bypass Register• Device Identification Reg

205ATmega162/V2513E–AVR–09/03on the Fuse settings for the clock options, the part will remain reset for a Reset Time-outPeriod (refer to “Clock Source

206ATmega162/V2513E–AVR–09/03IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID-register as data register. The ID-Regis-ter consists of a v

207ATmega162/V2513E–AVR–09/03If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should beset to one. The reason for this i

208ATmega162/V2513E–AVR–09/03Figure 87. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.DQ DQG0101DQ DQG01010101DQ DQG01Port Pin

209ATmega162/V2513E–AVR–09/03Figure 88. General Port Pin Schematic DiagramScanning the RESET pin The RESET pin accepts 5V active low logic for standa

21ATmega162/V2513E–AVR–09/03The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interr

210ATmega162/V2513E–AVR–09/03Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RCOscillator, Ex

211ATmega162/V2513E–AVR–09/03Scanning the Analog ComparatorThe relevant Comparator signals regarding Boundary-scan are shown in Figure 91. TheBoundary

212ATmega162/V2513E–AVR–09/03ATmega162 Boundary-scan OrderTable 88 shows the Scan order between TDI and TDO when the Boundary-scan chainis selected as

213ATmega162/V2513E–AVR–09/0387 PB5.Data Port B86 PB5.Control85 PB5.Pullup_Enable84 PB6.Data83 PB6.Control82 PB6.Pullup_Enable81 PB7.Data80 PB7.Contro

214ATmega162/V2513E–AVR–09/0351 PD7.Pullup_Enable Port D50 EXTCLKEN Enable signals for main Clock/Oscillators49 OSCON48 OSC32EN47 EXTCLK (XTAL1) Clock

215ATmega162/V2513E–AVR–09/03Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.Boundary-scan Description Language FilesBoundary-scan Descri

216ATmega162/V2513E–AVR–09/03Boot Loader Support – Read-While-Write Self-programmingThe Boot Loader Support provides a real Read-While-Write Self-prog

217ATmega162/V2513E–AVR–09/03Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software o

218ATmega162/V2513E–AVR–09/03Figure 94. Memory Sections(1)Note: 1. The parameters are given in Table 94 on page 228.Boot Loader Lock Bits If no Boot

219ATmega162/V2513E–AVR–09/03ming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock(Lock bit mode 1) does not control rea

22ATmega162/V2513E–AVR–09/03The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are contro

220ATmega162/V2513E–AVR–09/03Entering the Boot Loader ProgramEntering the Boot Loader takes place by a jump or call from the application program.This

221ATmega162/V2513E–AVR–09/03• Bit 3 – BLBSET: Boot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction with

222ATmega162/V2513E–AVR–09/03Addressing the Flash During Self-programmingThe Z-pointer is used to address the SPM commands.Since the Flash is organize

223ATmega162/V2513E–AVR–09/03Self-programming the FlashThe program memory is updated in a page by page fashion. Before programming apage with the data

224ATmega162/V2513E–AVR–09/03Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interruptwhen the SPM

225ATmega162/V2513E–AVR–09/03executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM willwork as described in the Instruction set Manu

226ATmega162/V2513E–AVR–09/033. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to dec

227ATmega162/V2513E–AVR–09/03ldi looplo, low(PAGESIZEB) ;init loop variableldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256subi YL, low

228ATmega162/V2513E–AVR–09/03ATmega162 Boot Loader ParametersIn Table 94 through Table 96, the parameters used in the description of the self pro-gram

229ATmega162/V2513E–AVR–09/03Note: 1. Z15:Z14: always ignoredZ0: should be zero for all SPM commands, byte select for the LPM instruction.See “Address

23ATmega162/V2513E–AVR–09/03Keep the AVR RESET active (low) during periods of insufficient power supply voltage.This can be done by enabling the inter

230ATmega162/V2513E–AVR–09/03Memory ProgrammingProgram And Data Memory Lock BitsThe ATmega162 provides six Lock bits which can be left unprogrammed (“

231ATmega162/V2513E–AVR–09/03Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.2. “1” means unprogrammed, “0” mean

232ATmega162/V2513E–AVR–09/03Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.2. The default value of BOOTSZ1:0 results in ma

233ATmega162/V2513E–AVR–09/03Latching of Fuses The Fuse values are latched when the device enters Programming mode and changesof the Fuse values will

234ATmega162/V2513E–AVR–09/03Table 102. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O FunctionRDY/BSY PD1 O0: Device is busy programm

235ATmega162/V2513E–AVR–09/03Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply

236ATmega162/V2513E–AVR–09/03Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lockbits are not reset until th

237ATmega162/V2513E–AVR–09/03While the lower bits in the address are mapped to words within the page, the higher bitsaddress the pages within the FLAS

238ATmega162/V2513E–AVR–09/03Figure 98. Programming the Flash WaveformsNote: “XX” is don’t care. The letters refer to the programming description abo

239ATmega162/V2513E–AVR–09/03Figure 99. Programming the EEPROM WaveformsReading the Flash The algorithm for reading the Flash memory is as follows (r

24ATmega162/V2513E–AVR–09/03External Memory InterfaceWith all the features the External Memory Interface provides, it is well suited to operateas an i

240ATmega162/V2513E–AVR–09/03Programming the Fuse High BitsThe algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe Fl

241ATmega162/V2513E–AVR–09/03Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming theFlash” on p

242ATmega162/V2513E–AVR–09/03Reading the Calibration Byte The algorithm for reading the calibration byte is as follows (refer to “Programming theFlash

243ATmega162/V2513E–AVR–09/03Figure 104. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)Note: 1. The

244ATmega162/V2513E–AVR–09/03Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write LockBits commands.2. tWLRH_CE is

245ATmega162/V2513E–AVR–09/03Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the serial clock (SCK) input

246ATmega162/V2513E–AVR–09/036. Any memory location can be verified by using the Read instruction which returns the content at the selected address at

247ATmega162/V2513E–AVR–09/03Table 111. SPI Serial Programming Instruction Set(1) Instruction Instruction Format OperationByte 1 Byte 2 Byte 3 Byte4P

248ATmega162/V2513E–AVR–09/03Note: 1. a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don

249ATmega162/V2513E–AVR–09/03Programming via the JTAG InterfaceProgramming through the JTAG interface requires control of the four JTAG specificpins:

25ATmega162/V2513E–AVR–09/03The control bits for the External Memory Interface are located in three registers, theMCU Control Register – MCUCR, the Ex

250ATmega162/V2513E–AVR–09/03Figure 107. State machine sequence for changing the instruction wordTest-Logic-ResetRun-Test/IdleShift-DRExit1-DRPause-D

251ATmega162/V2513E–AVR–09/03AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset modeor taking the device

252ATmega162/V2513E–AVR–09/03Data Registers The Data Registers are selected by the JTAG Instruction Registers described in section“Programming Specifi

253ATmega162/V2513E–AVR–09/03Programming Command RegisterThe Programming Command Register is a 15-bit register. This register is used to seri-ally shi

254ATmega162/V2513E–AVR–09/03Table 112. JTAG Programming Instruction Set Instruction TDI sequence TDO sequence Notes1a. Chip eRase 0100011_1000000001

255ATmega162/V2513E–AVR–09/035d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_oooooooo6a. En

256ATmega162/V2513E–AVR–09/03Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (whic

257ATmega162/V2513E–AVR–09/03Figure 110. State Machine Sequence for Changing/Reading the Data WordVirtual Flash Page Load RegisterThe Virtual Flash P

258ATmega162/V2513E–AVR–09/03Figure 111. Virtual Flash Page Load RegisterVirtual Flash Page Read RegisterThe Virtual Flash Page Read Register is a vi

259ATmega162/V2513E–AVR–09/03Figure 112. Virtual Flash Page Read RegisterProgramming Algorithm All references below of type “1a”, “1b”, and so on, re

26ATmega162/V2513E–AVR–09/03Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port reg-ister is wr

260ATmega162/V2513E–AVR–09/038. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 108 on page 24

261ATmega162/V2513E–AVR–09/03Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See “PerformingChip Erase” on page 2

262ATmega162/V2513E–AVR–09/03Reading the Fuses and Lock Bits1. Enter JTAG instruction PROG_COMMANDS.2. Enable Fuse/Lock bit read using programming ins

263ATmega162/V2513E–AVR–09/03Electrical CharacteristicsDC CharacteristicsAbsolute Maximum Ratings*Operating Temperature...

264ATmega162/V2513E–AVR–09/03Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value wher

265ATmega162/V2513E–AVR–09/03Figure 113. Absolute Maximum Frequency as a function of VCC, ATmega162VFigure 114. Absolute Maximum Frequency as a func

266ATmega162/V2513E–AVR–09/03External Clock Drive WaveformsFigure 115. External Clock Drive WaveformsExternal Clock DriveVIL1VIH1Table 113. External

267ATmega162/V2513E–AVR–09/03SPI Timing CharacteristicsSee Figure 116 and Figure 117 for details.Note: 1. In SPI Programming mode, the minimum SCK hig

268ATmega162/V2513E–AVR–09/03Figure 117. SPI Interface Timing Requirements (Slave Mode)MISO(Data Output)SCK(CPOL = 1)MOSI(Data Input)SCK(CPOL = 0)SSM

269ATmega162/V2513E–AVR–09/03External Data Memory TimingNotes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the

27ATmega162/V2513E–AVR–09/03Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (low

270ATmega162/V2513E–AVR–09/03Table 117. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0Symbol Parameter4 MHz Oscillator V

271ATmega162/V2513E–AVR–09/03Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2. Th

272ATmega162/V2513E–AVR–09/03Figure 118. External Memory Timing (SRWn1 = 0, SRWn0 = 0Figure 119. External Memory Timing (SRWn1 = 0, SRWn0 = 1)ALET1

273ATmega162/V2513E–AVR–09/03Figure 120. External Memory Timing (SRWn1 = 1, SRWn0 = 0)Figure 121. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)No

274ATmega162/V2513E–AVR–09/03ATmega162 Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-fac

275ATmega162/V2513E–AVR–09/03Figure 123. Active Supply Current vs. Frequency (1 - 20 MHz)Figure 124. Active Supply Current vs. VCC (Internal RC Osci

276ATmega162/V2513E–AVR–09/03Figure 125. Active Supply Current vs. VCC (32 kHz External Oscillator)Idle Supply Current Figure 126. Idle Supply Curre

277ATmega162/V2513E–AVR–09/03Figure 127. Idle Supply Current vs. Frequency (1 - 20 MHz)Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillat

278ATmega162/V2513E–AVR–09/03Figure 129. Idle Supply Current vs. VCC (32 kHz External Oscillator)Power-down Supply Current Figure 130. Power-down Su

279ATmega162/V2513E–AVR–09/03Figure 131. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)Power-save Supply Current Figure 132. Power-save

28ATmega162/V2513E–AVR–09/03Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (low

280ATmega162/V2513E–AVR–09/03Standby Supply Current Figure 133. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog TimerDisabled)Figure 134.

281ATmega162/V2513E–AVR–09/03Figure 135. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog TimerDisabled)Figure 136. Standby Supply Current

282ATmega162/V2513E–AVR–09/03Figure 137. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog TimerDisabled)Figure 138. Standby Supply Current

283ATmega162/V2513E–AVR–09/03Figure 139. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog TimerDisabled)Figure 140. Standby Supply Current

284ATmega162/V2513E–AVR–09/03Pin Pull-up Figure 141. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)Figure 142. I/O Pin Pull-up Resist

285ATmega162/V2513E–AVR–09/03Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)Figure 144. Reset Pull-up Resistor Current v

286ATmega162/V2513E–AVR–09/03Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)Figure 146. Reset Pull-up Resistor Current

287ATmega162/V2513E–AVR–09/03Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V)Figure 148. I/O Pin Source Current

288ATmega162/V2513E–AVR–09/03Figure 149. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V)Figure 150. I/O Pin Sink Current vs. Output Voltage (

289ATmega162/V2513E–AVR–09/03Figure 151. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)Figure 152. I/O Pin Sink Current vs. Output Voltage (VC

29ATmega162/V2513E–AVR–09/03SRAM address space is configured as one sector, the wait-states are configured by theSRW11 and SRW10 bits.• Bit 1 and Bit

290ATmega162/V2513E–AVR–09/03Pin Thresholds and HysteresisFigure 153. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)Figure 154.

291ATmega162/V2513E–AVR–09/03Figure 155. I/O Pin Input Hysteresis vs. VCC Figure 156. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as

292ATmega162/V2513E–AVR–09/03Figure 157. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)Figure 158. Reset Input Pin Hysteresis vs

293ATmega162/V2513E–AVR–09/03BOD Thresholds and Analog Comparator OffsetFigure 159. BOD Thresholds vs. Temperature (BOD Level is 4.3V)Figure 160. BO

294ATmega162/V2513E–AVR–09/03Figure 161. BOD Thresholds vs. Temperature (BOD Level is 2.3V)Figure 162. BOD Thresholds vs. Temperature (BOD Level is

295ATmega162/V2513E–AVR–09/03Figure 163. Bandgap Voltage vs. VCC Figure 164. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)BAND

296ATmega162/V2513E–AVR–09/03Figure 165. Analog Comparator Offset Voltage vs. Common Mode Voltage(VCC=2.7V)Internal Oscillator Speed Figure 166. Wat

297ATmega162/V2513E–AVR–09/03Figure 167. Calibrated 8 MHz RC Oscillator Frequency vs. TemperatureFigure 168. Calibrated 8 MHz RC Oscillator Frequenc

298ATmega162/V2513E–AVR–09/03Figure 169. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal ValueCurrent Consumption of Peripheral UnitsFigure 170.

299ATmega162/V2513E–AVR–09/03Figure 171. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled)Figure 172. Watchdog TImer Current vs. VCC 32kHz TOSC

3ATmega162/V2513E–AVR–09/03Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing p

30ATmega162/V2513E–AVR–09/03Special Function IO Register – SFIOR• Bit 6 – XMBK: External Memory Bus Keeper EnableWriting XMBK to one enables the Bus K

300ATmega162/V2513E–AVR–09/03Figure 173. Analog Comparator Current vs. VCC Figure 174. Programming Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC

301ATmega162/V2513E–AVR–09/03Current Consumption in Reset and Reset PulsewidthFigure 175. Reset Supply Current vs. Frequency (0.1 - 1.0 MHz, Excludin

302ATmega162/V2513E–AVR–09/03Figure 177. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC050010001500200025001.5 2 2.5 3 3.5 4 4.5 5 5.5VCC (V)Pul

303ATmega162/V2513E–AVR–09/03Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(0xFF) Reserved – – – – – – – –.. Reserv

304ATmega162/V2513E–AVR–09/03(0x60) Reserved – – – – – – – –0x3F (0x5F) SREG I T H S V N Z C 80x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 11

305ATmega162/V2513E–AVR–09/03Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug

306ATmega162/V2513E–AVR–09/03Instruction Set SummaryMnemonicsOperands Description OperationFlags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Ad

307ATmega162/V2513E–AVR–09/03BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2BRID k Branch if Interrupt Disabled if ( I

308ATmega162/V2513E–AVR–09/03CLHClear Half Carry Flag in SREGH ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific descr.

309ATmega162/V2513E–AVR–09/03Ordering InformationNotes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales offic

31ATmega162/V2513E–AVR–09/03When the device is set in ATmega161 compatibility mode, the internal address space is1,120 bytes. This implies that the fi

310ATmega162/V2513E–AVR–09/03Packaging Information44A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm Body S

311ATmega162/V2513E–AVR–09/0340P6 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic D

312ATmega162/V2513E–AVR–09/0344M1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50

313ATmega162/V2513E–AVR–09/03Erratas The revision letter in this section refers to the revision of the ATmega162 device.ATmega162, all rev. There are

314ATmega162/V2513E–AVR–09/03Datasheet Change Log for ATmega162Please note that the referring page numbers in this section are referred to this docu-m

315ATmega162/V2513E–AVR–09/0312. Added information about PWM symmetry for Timer0 on page 97 and Timer2on page 146.13. Updated Table 18 on page 47, Tab

316ATmega162/V2513E–AVR–09/03

iATmega162/V2513E–AVR–09/03Table of Contents Features...

iiATmega162/V2513E–AVR–09/03Extended Standby Mode ... 43Minimizing Po

iiiATmega162/V2513E–AVR–09/038-bit Timer/Counter2 with PWM and Asynchronous operation... 137Overview...

32ATmega162/V2513E–AVR–09/03Using all 64KB Locations of External MemorySince the external memory is mapped after the internal memory as shown in Figur

ivATmega162/V2513E–AVR–09/03IEEE 1149.1 (JTAG) Boundary-scan ... 203Features...

vATmega162/V2513E–AVR–09/03Packaging Information... 31044A ...

viATmega162/V2513E–AVR–09/03

Printed on recycled paper.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Co

33ATmega162/V2513E–AVR–09/03System Clock and Clock OptionsClock Systems and their DistributionFigure 18 presents the principal clock systems in the AV

34ATmega162/V2513E–AVR–09/03Clock Sources The device has the following clock source options, selectable by Flash Fuse bits asshown below. The clock fr

35ATmega162/V2513E–AVR–09/03Figure 19. Crystal Oscillator ConnectionsThe Oscillator can operate in four different modes, each optimized for a specifi

36ATmega162/V2513E–AVR–09/03Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device, and only if

37ATmega162/V2513E–AVR–09/03Reset Time-out. For more information on the pre-programmed calibration value, see thesection “Calibration Byte” on page 23

38ATmega162/V2513E–AVR–09/03External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 20. To run the

39ATmega162/V2513E–AVR–09/03will be output also during Reset and the normal operation of PortB will be overriddenwhen the fuse is programmed. Any cloc

4ATmega162/V2513E–AVR–09/03The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly co

40ATmega162/V2513E–AVR–09/03The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-grammed, the CLKPS bits will be reset t

41ATmega162/V2513E–AVR–09/03Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving p

42ATmega162/V2513E–AVR–09/03Extended MCU Control Register – EMCUCR• Bit 7 – SM0: Sleep Mode Select Bit 0The Sleep Mode Select bits select between the

43ATmega162/V2513E–AVR–09/03Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enterPower-save mode. This mo

44ATmega162/V2513E–AVR–09/03Minimizing Power ConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR co

45ATmega162/V2513E–AVR–09/03the logic level, power consumption will increase. Note that the TDI pin for the nextdevice in the scan chain contains a pu

46ATmega162/V2513E–AVR–09/03System Control and ResetResetting the AVR During Reset, all I/O Registers are set to their initial values, and the program

47ATmega162/V2513E–AVR–09/03Figure 21. Reset LogicNote: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling)Pow

48ATmega162/V2513E–AVR–09/03Figure 22. MCU Start-up, RESET Tied to VCC.Figure 23. MCU Start-up, RESET Extended ExternallyExternal Reset An External

49ATmega162/V2513E–AVR–09/03Brown-out Detection ATmega162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during operatio

5ATmega162/V2513E–AVR–09/03ATmega161 Compatibility ModeProgramming the M161C will change the following functionality:• The extended I/O map will be co

50ATmega162/V2513E–AVR–09/03Figure 25. Brown-out Reset During OperationWatchdog Reset When the Watchdog times out, it will generate a short reset pul

51ATmega162/V2513E–AVR–09/03• Bit 2 – BORF: Brown-out Reset FlagThis bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or

52ATmega162/V2513E–AVR–09/03shown in Table 22. Safety level 0 corresponds to the setting in ATmega161. There is norestriction on enabling the WDT in a

53ATmega162/V2513E–AVR–09/03if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-ing procedure must be followed:1. In

54ATmega162/V2513E–AVR–09/03The following code example shows one assembly and one C function for turning off theWDT. The example assumes that interrup

55ATmega162/V2513E–AVR–09/03Timed Sequences for Changing the Configuration of the Watchdog TimerThe sequence for changing configuration differs slight

56ATmega162/V2513E–AVR–09/03Interrupts This section describes the specifics of the interrupt handling as performed inATmega162. For a general explanat

57ATmega162/V2513E–AVR–09/03Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loaderaddress at reset, see “Boot Loader S

58ATmega162/V2513E–AVR–09/03Table 26 shows Reset and Interrupt Vectors placement for the various combinations ofBOOTRST and IVSEL settings. If the pro

59ATmega162/V2513E–AVR–09/030x03A ldi r16,low(RAMEND)0x03B out SPL,r160x03C sei ; Enable interrupts0x03D <instr> xxx... ... ...When the BOOTRST

6ATmega162/V2513E–AVR–09/03Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Po

60ATmega162/V2513E–AVR–09/03When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and theIVSEL bit in the GICR Register is set be

61ATmega162/V2513E–AVR–09/03IVCE bit will disable interrupts, as explained in the IVSEL description above. See CodeExample below.Assembly Code Example

62ATmega162/V2513E–AVR–09/03I/O-PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This

63ATmega162/V2513E–AVR–09/03Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows afunct

64ATmega162/V2513E–AVR–09/03enabled state is fully acceptable, as a high-impedant environment will not notice the dif-ference between a strong high dr

65ATmega162/V2513E–AVR–09/03Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the c

66ATmega162/V2513E–AVR–09/03The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as

67ATmega162/V2513E–AVR–09/03Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a definedlevel. Even though mos

68ATmega162/V2513E–AVR–09/03Table 28 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 32 are not shown in the su

69ATmega162/V2513E–AVR–09/03Special Function IO Register – SFIOR• Bit 2 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the I/O

7ATmega162/V2513E–AVR–09/03AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is t

70ATmega162/V2513E–AVR–09/03Notes: 1. ADA is short for ADdress Active and represents the time when address is output. See“External Memory Interface” o

71ATmega162/V2513E–AVR–09/03Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 32.The alternate pin configurati

72ATmega162/V2513E–AVR–09/03OC3B, Output Compare Match B output: The PB4 pin can serve as an external outputfor the Timer/Counter3 Output Compare B. T

73ATmega162/V2513E–AVR–09/03 Notes: 1. CKOUT is one if the CKOUT Fuse is programmed.2. clkI/O is the divided system clock.Table 33. Overriding Signal

74ATmega162/V2513E–AVR–09/03Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 35. If the JTAG interface isenab

75ATmega162/V2513E–AVR–09/03• A13/TMS/PCINT13 – Port C, Bit 5A13, External memory interface address bit 13.TMS, JTAG Test Mode Select: This pin is use

76ATmega162/V2513E–AVR–09/03Notes: 1. PCINTn is Pin Change Interrupt Enable bit n.2. PCINTn is Pin Change Interrupt input n.Notes: 1. PCINTn is Pin Ch

77ATmega162/V2513E–AVR–09/03Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 38.The alternate pin configurati

78ATmega162/V2513E–AVR–09/03• TOSC1/XCK0/OC3A – Port D, Bit 4TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-chron

79ATmega162/V2513E–AVR–09/03• RXD0 – Port D, Bit 0RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver isenabled this pin is confi

8ATmega162/V2513E–AVR–09/03Six of the 32 registers can be used as three 16-bit indirect address register pointers forData Space addressing – enabling

80ATmega162/V2513E–AVR–09/03Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 41.The alternate pin configurati

81ATmega162/V2513E–AVR–09/03Register Description for I/O-PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Addre

82ATmega162/V2513E–AVR–09/03Port C Input Pins Address – PINCPort D Data Register – PORTDPort D Data Direction Register – DDRDPort D Input Pins Address

83ATmega162/V2513E–AVR–09/03External Interrupts The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of thePCINT15..0 pins. Obser

84ATmega162/V2513E–AVR–09/03• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the external

85ATmega162/V2513E–AVR–09/03General Interrupt Control Register – GICR• Bit 7 – INT1: External Interrupt Request 1 EnableWhen the INT1 bit is set (one)

86ATmega162/V2513E–AVR–09/03General Interrupt Flag Register – GIFR• Bit 7 – INTF1: External Interrupt Flag 1When an edge or logic change on the INT1 p

87ATmega162/V2513E–AVR–09/03Pin Change Mask Register 1 – PCMSK1• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8Each PCINT15..8 bit selects whethe

88ATmega162/V2513E–AVR–09/038-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain feat

89ATmega162/V2513E–AVR–09/03inactive when no clock source is selected. The output from the clock select logic isreferred to as the timer clock (clkT0)

9ATmega162/V2513E–AVR–09/03The AVR Status Register – SREG – is defined as:• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be

90ATmega162/V2513E–AVR–09/03Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 34 shows a bl

91ATmega162/V2513E–AVR–09/03Figure 35 shows a block diagram of the output compare unit. Figure 35. Output Compare Unit, Block DiagramThe OCR0 Registe

92ATmega162/V2513E–AVR–09/03Using the Output Compare UnitSince writing TCNT0 in any mode of operation will block all compare matches for onetimer cloc

93ATmega162/V2513E–AVR–09/03The design of the output compare pin logic allows initialization of the OC0 state beforethe output is enabled. Note that s

94ATmega162/V2513E–AVR–09/03Figure 37. CTC Mode, Timing DiagramAn interrupt can be generated each time the counter value reaches the TOP value byusin

95ATmega162/V2513E–AVR–09/03non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0slopes represent compare matches betwee

96ATmega162/V2513E–AVR–09/03Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correctPWM waveform gener

97ATmega162/V2513E–AVR–09/03between OCR0 and TCNT0 when the counter decrements. The PWM frequency for theoutput when using phase correct PWM can be ca

98ATmega162/V2513E–AVR–09/03Figure 41. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 42 shows the setting of OCF0 in all modes exce

99ATmega162/V2513E–AVR–09/038-bit Timer/Counter Register DescriptionTimer/Counter Control Register – TCCR0• Bit 7 – FOC0: Force Output CompareThe FOC0