Rainbow-electronics ATmega64M1 Uživatelský manuál stáhnout pdf (Strana 123)

100

101

123

8209A–AVR–08/09

ATmega16M1/32M1/64M1

Figure 16-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f

clk_I/O

/8)

Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOVn Flag at BOTTOM.

Figure 16-12. Timer/Counter Timing Diagram, no Prescaling

Figure 16-13 shows the same timing data, but with the prescaler enabled.

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clk

I/O

/8)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clk

I/O

/1)

clk

I/O

1 2 ... 118 119 120 121 122 123 124 125 126 127 128 ... 342 343

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