Rainbow-electronics ATtiny26L Uživatelský manuál

1Features• High-performance, Low-power AVR ® 8-bit Microcontroller• RISC Architecture– 118 Powerful Instructions – Most Single Clock Cycle Execution–

10ATtiny26(L) 1477B–AVR–04/02Program and Data Addressing ModesThe ATtiny26/L AVR Enhanced RISC microcontroller supports powerful and efficientaddressi

100ATtiny26(L) 1477B–AVR–04/02Alternate Functions Of Port B Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI pro-gram

101ATtiny26(L)1477B–AVR–04/02PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when globalinterrupt is enabled, pin change in

102ATtiny26(L) 1477B–AVR–04/02• OC1B/PCINT0 – Port B, Bit 3OC1B: Output Compare match output: The PB3 pin can serve as an output for theTimer/Counter1

103ATtiny26(L)1477B–AVR–04/02• DI/SDA/OC1A/PCINT0 – Port B, Bit 0DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normalpo

104ATtiny26(L) 1477B–AVR–04/02Notes: 1. Enabling of the Timer/Counter1 Compare match outputs and Timer/Counter1 PWM Outputs OC1A/OC1B and OC1A/OC1Bare

105ATtiny26(L)1477B–AVR–04/02Register Description for I/O PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Addr

106ATtiny26(L) 1477B–AVR–04/02Memory ProgrammingProgram and Data Memory Lock BitsThe ATtiny26 provides two Lock bits which can be left unprogrammed (“

107ATtiny26(L)1477B–AVR–04/02Fuse Bits The ATtiny26 has two Fuse bytes. Table 49 and Table 50 describe briefly the functional-ity of all the fuses and

108ATtiny26(L) 1477B–AVR–04/02Latching of Fuses The fuse values are latched when the device enters programming mode and changes ofthe fuse values will

109ATtiny26(L)1477B–AVR–04/02Figure 58. Parallel ProgrammingNote: 1. The pin is used for two different control signals. In the description below, nor

11ATtiny26(L)1477B–AVR–04/02I/O Direct Figure 8. I/O Direct AddressingOperand address is contained in 6 bits of the instruction word. n is the destin

110ATtiny26(L) 1477B–AVR–04/02Note: 1. [XA1, XA0] = 0b11 is “No Action, Idle”. As long as XTAL1 is not pulsed, the Com-mand, Address, and Data Registe

111ATtiny26(L)1477B–AVR–04/02Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in parallel programming mode:1. Apply

112ATtiny26(L) 1477B–AVR–04/02Programming the Flash The Flash is organized in pages, see Table 55 on page 110. When programming theFlash, the program

113ATtiny26(L)1477B–AVR–04/02F. Load Address High byte1. Set XA1, XA0 to “00”. This enables address loading.2. Set BS1 to “1”. This selects high addre

114ATtiny26(L) 1477B–AVR–04/02Figure 60. Programming the Flash Waveforms(1)Note: 1. “XX” is don’t care. The letters refer to the programming descript

115ATtiny26(L)1477B–AVR–04/02Figure 61. Programming the EEPROM WaveformsReading the Flash The algorithm for reading the Flash memory is as follows (r

116ATtiny26(L) 1477B–AVR–04/02Programming the Fuse High BitsThe algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe F

117ATtiny26(L)1477B–AVR–04/02Figure 63. Mapping Between BS1, BS2 and the Fuse- and Lock-bits During ReadReading the Signature Bytes The algorithm for

118ATtiny26(L) 1477B–AVR–04/02Figure 65. Parallel Programming Timing, Loading Sequence with TimingRequirements(1)Note: 1. The timing requirements sho

119ATtiny26(L)1477B–AVR–04/02Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2. tWLRH_CE is

12ATtiny26(L) 1477B–AVR–04/02Operand address is the result of the Y- or Z-register contents added to the address con-tained in 6 bits of the instructi

120ATtiny26(L) 1477B–AVR–04/02Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pull

121ATtiny26(L)1477B–AVR–04/02Serial Programming AlgorithmWhen writing serial data to the ATtiny26, data is clocked on the rising edge of SCK.When read

122ATtiny26(L) 1477B–AVR–04/02Data Polling Flash When a page is being programmed into the Flash, reading an address location withinthe page being prog

123ATtiny26(L)1477B–AVR–04/02Note: a = address high bitsb = address low bitsH = 0 – Low byte, 1 – High Byteo = data outi = data inx = don’t careTable

124ATtiny26(L) 1477B–AVR–04/02Serial Programming CharacteristicsFigure 69. Serial Programming TimingNote: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for

125ATtiny26(L)1477B–AVR–04/02Electrical CharacteristicsAbsolute Maximum Ratings* Operating Temperature... -55°C to +125

126ATtiny26(L) 1477B–AVR–04/02Notes: 1. Typical values contained in this data sheet are based on simulations and characterization of other AVR microco

127ATtiny26(L)1477B–AVR–04/02External Clock Drive WaveformsFigure 70. External Clock Drive WaveformsExternal Clock DriveVIL1VIH1Table 62. External C

128ATtiny26(L) 1477B–AVR–04/02ADC Characteristics – Preliminary DataNotes: 1. Values aren guidelines only. Actual values are TBD.2. Minimum for AVCC i

129ATtiny26(L)1477B–AVR–04/02ATtiny26 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not test

13ATtiny26(L)1477B–AVR–04/02The X-, Y-, or Z-register is incremented after the operation. Operand address is the con-tent of the X-, Y-, or Z-register

130ATtiny26(L) 1477B–AVR–04/02Figure 71. RC Oscillator Frequency vs. Temperature (the devices are calibrated to1 MHz at Vcc = 5V, T=25c)Figure 72. R

131ATtiny26(L)1477B–AVR–04/02Figure 73. RC Oscillator Frequency vs Temperature (the devices are calibrated to2 MHz at Vcc = 5V, T=25c)Figure 74. RC

132ATtiny26(L) 1477B–AVR–04/02Figure 75. RC Oscillator Frequency vs Temperature (the devices are calibrated to4 MHz at Vcc = 5V, T=25c)Figure 76. RC

133ATtiny26(L)1477B–AVR–04/02Figure 77. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8MHz at Vcc = 5V, T=25c)Figure 78. RC

134ATtiny26(L) 1477B–AVR–04/02Figure 79. RC Oscillator Frequency vs. Temperature (the devices are calibrated to1 MHz at Vcc = 5V, T=25c)Figure 80. R

135ATtiny26(L)1477B–AVR–04/02Figure 81. RC Oscillator Frequency vs. Temperature (the devices are calibrated to2 MHz at Vcc = 5V, T=25c)Figure 82. RC

136ATtiny26(L) 1477B–AVR–04/02Figure 83. RC Oscillator Frequency vs. Temperature (the devices are calibrated to4 MHz at Vcc = 5V, T=25c)Figure 84. R

137ATtiny26(L)1477B–AVR–04/02Figure 85. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8MHz at Vcc = 5V, T=25c)Figure 86. RC

138ATtiny26(L) 1477B–AVR–04/02ATtiny26/L Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z

139ATtiny26(L)1477B–AVR–04/02Instruction Set Summary Mnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr

14ATtiny26(L) 1477B–AVR–04/02Relative Program Addressing, RJMP and RCALLFigure 16. Relative Program Memory AddressingProgram execution continues at a

140ATtiny26(L) 1477B–AVR–04/02LD Rd, Y Load Indirect Rd ← (Y) None 2LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2LD Rd, -Y Load Ind

141ATtiny26(L)1477B–AVR–04/02Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed orderi

142ATtiny26(L) 1477B–AVR–04/02Packaging Information20P3 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20P3, 20-lead (0.300"/7.

143ATtiny26(L)1477B–AVR–04/0220S7.60 (0.2992)7.40 (0.2914)0.51(0.020)0.33(0.013)10.65 (0.419)10.00 (0.394)PIN 1 ID1.27 (0.050) BSC13.00 (0.5118)12.60

144ATtiny26(L) 1477B–AVR–04/0232M1-APIN 1 ID 2325 Orchard Parkway San Jose, CA 95131TITLE32M1-ARDRAWING NO. REV R32M1-A, 32-pad, 5x5x1.0m

145ATtiny26(L)1477B–AVR–04/02Data Sheet Change Log for ATtiny26Please note that the referring page numbers in this section are referred to this docu-m

146ATtiny26(L) 1477B–AVR–04/02

iATtiny26(L)1477B–AVR–04/02Table of Contents Features...

iiATtiny26(L) 1477B–AVR–04/02Universal Serial Interface – USI... 63Overview...

iiiATtiny26(L)1477B–AVR–04/02Ordering Information(1)... 141Packaging Information ..

15ATtiny26(L)1477B–AVR–04/02Memory Access Times and Instruction Execution TimingThis section describes the general access timing concepts for instruct

ivATtiny26(L) 1477B–AVR–04/02

Printed on recycled paper.1477B–AVR–04/020M© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those

16ATtiny26(L) 1477B–AVR–04/02Figure 19. On-chip Data SRAM Access CyclesSystem Clock ØWRRDDataDataAddressAddressT1 T2 T3 T4Prev. AddressReadWrite

17ATtiny26(L)1477B–AVR–04/02I/O Memory The I/O space definition of the ATtiny26/L is shown in Table 1Table 1. ATtiny26/L I/O Space(1) Address Hex Nam

18ATtiny26(L) 1477B–AVR–04/02Note: 1. Reserved and unused locations are not shown in the table.All ATtiny26/L I/O and peripheral registers are placed

19ATtiny26(L)1477B–AVR–04/02• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result after the different arithmetic and logicoperatio

2ATtiny26(L) 1477B–AVR–04/02Pin ConfigurationDisclaimer Typical values contained in this data sheet are based on simulations and characteriza-tion of

20ATtiny26(L) 1477B–AVR–04/02Reset and Interrupt HandlingThe ATtiny26/L provides eleven interrupt sources. These interrupts and the separateReset Vect

21ATtiny26(L)1477B–AVR–04/02Reset Sources The ATtiny26/L provides four sources of reset:• Power-on Reset. The MCU is reset when the supply voltage is

22ATtiny26(L) 1477B–AVR–04/020Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling)2. VBOT may be below no

23ATtiny26(L)1477B–AVR–04/02Figure 21. MCU Start-up, RESET Tied to VCCFigure 22. MCU Start-up, RESET Controlled ExternallyExternal Reset An External

24ATtiny26(L) 1477B–AVR–04/02Brown-out Detection ATtiny26/L has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during the op

25ATtiny26(L)1477B–AVR–04/02System Clock and Clock OptionsClock Systems and their DistributionFigure 26 presents the principal clock systems in the AV

26ATtiny26(L) 1477B–AVR–04/02Internal PLL for Fast Peripheral Clock Generation – clkPCKThe internal PLL in ATtiny26/L generates a clock frequency that

27ATtiny26(L)1477B–AVR–04/02Clock Sources The device has the following clock source options, selectable by Flash Fuse bits asshown below on Table 4. T

28ATtiny26(L) 1477B–AVR–04/02each time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltagedependent as shown in the Electrica

29ATtiny26(L)1477B–AVR–04/02The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shownin Table 8.Notes: 1. These options shoul

3ATtiny26(L)1477B–AVR–04/02Description The ATtiny26/L is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executi

30ATtiny26(L) 1477B–AVR–04/02External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 29can be used.

31ATtiny26(L)1477B–AVR–04/02Calibrated Internal RC OscillatorThe calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. A

32ATtiny26(L) 1477B–AVR–04/02oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values isnot guaranteed, as indicate

33ATtiny26(L)1477B–AVR–04/02High Frequency PLL Clock – PLLCLKThere is an internal PLL that provides nominally 64 MHz clock rate locked to the RCOscill

34ATtiny26(L) 1477B–AVR–04/02Interrupt Handling The ATtiny26/L has two 8-bit Interrupt Mask Control Registers; GIMSK – General Inter-rupt Mask Registe

35ATtiny26(L)1477B–AVR–04/02The corresponding interrupt of External Interrupt Request 0 is executed from programmemory address $001. See also “Externa

36ATtiny26(L) 1477B–AVR–04/02Timer/Counter Interrupt Mask Register – TIMSK• Bit 7 – Res: Reserved BitThis bit is a reserved bit in the ATtiny26/L and

37ATtiny26(L)1477B–AVR–04/02Timer/Counter Interrupt Flag Register – TIFR• Bit 7 – Res: Reserved BitThis bit is a reserved bit in the ATtiny26/L and al

38ATtiny26(L) 1477B–AVR–04/02External Interrupt The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interruptwill trigg

39ATtiny26(L)1477B–AVR–04/02Notes: 1. Each line represents a bit or fuse combination which enables the function.2. A fuse value of “0” is programmed,

4ATtiny26(L) 1477B–AVR–04/02Block Diagram Figure 1. The ATtiny26/L Block DiagramWATCHDOGTIMERMCU CONTROLREGISTERUNIVERSALSERIALINTERFACETIMER/COUNTER

40ATtiny26(L) 1477B–AVR–04/02• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the externa

41ATtiny26(L)1477B–AVR–04/02Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving p

42ATtiny26(L) 1477B–AVR–04/02Note that if a level triggered external interrupt or pin change interrupt is used fromPower-down mode, the changed level

43ATtiny26(L)1477B–AVR–04/02Minimizing Power ConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR co

44ATtiny26(L) 1477B–AVR–04/02Timer/Counters The ATtiny26/L provides two general purpose 8-bit Timer/Counters. TheTimer/Counters have separate prescali

45ATtiny26(L)1477B–AVR–04/02Timer/Counter1 PrescalerFigure 32 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selectionsare between P

46ATtiny26(L) 1477B–AVR–04/02Figure 33. Timer/Counter0 Block DiagramTimer/Counter0 Control Register – TCCR0• Bits 7..4 – Res: Reserved BitsThese bits

47ATtiny26(L)1477B–AVR–04/02• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0The Clock Select0 bits 2, 1, and 0 define the prescaling

48ATtiny26(L) 1477B–AVR–04/02Figure 34. Timer/Counter1 Synchronization Register Block DiagramTimer/Counter1 and the prescaler allow running the CPU f

49ATtiny26(L)1477B–AVR–04/02Figure 35. Timer/Counter1 Block DiagramThree status flags (overflow and compare matches) are found in the Timer/CounterIn

5ATtiny26(L)1477B–AVR–04/02Pin DescriptionsVCC Digital supply voltage pin.GND Digital ground pin.AVCC AVCC is the supply voltage pin for Port A and th

50ATtiny26(L) 1477B–AVR–04/02Timer/Counter1 Control Register A – TCCR1A• Bits 7, 6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0The COM1A1

51ATtiny26(L)1477B–AVR–04/02• Bit 2 – FOC1B: Force Output Compare Match 1BWriting a logical one to this bit forces a change in the Compare Match outpu

52ATtiny26(L) 1477B–AVR–04/02• Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0The Clock Select bits 3, 2, 1, and 0 define the pre

53ATtiny26(L)1477B–AVR–04/02ware write that sets TCNT1 and OCR1A to the same value does not generate acompare match.A compare match will set the compa

54ATtiny26(L) 1477B–AVR–04/02• Bit 1 – PLLE: PLL EnableWhen the PLLE is set, the PLL is started and if needed internal RC Oscillator is startedas a PL

55ATtiny26(L)1477B–AVR–04/02Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B,the data value is first transferred to a tem

56ATtiny26(L) 1477B–AVR–04/02In PWM mode, the Timer Overflow Flag – TOV1, is set as in normal Timer/Countermode. Timer Overflow Interrupt1 operates ex

57ATtiny26(L)1477B–AVR–04/02Table 27. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) Clock Selection CS13..CS10 OC

58ATtiny26(L) 1477B–AVR–04/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical v

59ATtiny26(L)1477B–AVR–04/021. In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set

6ATtiny26(L) 1477B–AVR–04/02Architectural OverviewThe fast-access Register File concept contains 32 x 8-bit general purpose working reg-isters with a

60ATtiny26(L) 1477B–AVR–04/02EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.The write access time is typically 8.

61ATtiny26(L)1477B–AVR–04/02• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt i

62ATtiny26(L) 1477B–AVR–04/02Note: 1. Uses 1 MHz clock, independent of CKSEL-Fuse settings.Preventing EEPROM CorruptionDuring periods of low VCC, the

63ATtiny26(L)1477B–AVR–04/02Universal Serial Interface – USIThe Universal Serial Interface, or USI, provides the basic hardware resources neededfor se

64ATtiny26(L) 1477B–AVR–04/02Register DescriptionsUSI Data Register – USIDRThe USI uses no buffering of the serial register, i.e., when accessing the

65ATtiny26(L)1477B–AVR–04/02the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is writtento the USIOIF bit. Clearing thi

66ATtiny26(L) 1477B–AVR–04/02• Bit 5..4 – USIWM1..0: Wire ModeThese bits set the type of wire mode to be used. Basically only the function of theoutpu

67ATtiny26(L)1477B–AVR–04/02• Bit 3..2 – USICS1..0: Clock Source SelectThese bits set the clock source for the Shift Register and counter. The data ou

68ATtiny26(L) 1477B–AVR–04/02Functional DescriptionsThree-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode

69ATtiny26(L)1477B–AVR–04/02shifted by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the oppo-site edges versus mode 0, i.e., sample

7ATtiny26(L)1477B–AVR–04/02pipelining. While one instruction is being executed, the next instruction is pre-fetchedfrom the program memory. This conce

70ATtiny26(L) 1477B–AVR–04/02The following code demonstrates how to use the USI module as a SPI Master with max-imum speed (fsck = fck/2):SPITransfer_

71ATtiny26(L)1477B–AVR–04/02Note that the first two instructions is for initialization only and needs only to be executedonce.These instructions sets

72ATtiny26(L) 1477B–AVR–04/02Figure 43. Two-wire Mode, Typical Timing DiagramReferring to the timing diagram (Figure 43.), a bus transfer involves th

73ATtiny26(L)1477B–AVR–04/02Start Condition Detector The start condition detector is shown in Figure 44. The SDA line is delayed (in the rangeof 50 to

74ATtiny26(L) 1477B–AVR–04/02Analog Comparator The Analog Comparator compares the input values on the positive pin PA6 (AIN0) andnegative pin PA7 (AIN

75ATtiny26(L)1477B–AVR–04/02• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrupt

76ATtiny26(L) 1477B–AVR–04/02Notes: 1. MUX4 does not affect Analog Comparator input selection.2. Pin change interrupt on PA6 and PA7 is disabled if th

77ATtiny26(L)1477B–AVR–04/02Analog to Digital ConverterFeatures • 10-bit Resolution• ±2 LSB Absolute Accuracy• 0.5 LSB Integral Non-linearity• Optiona

78ATtiny26(L) 1477B–AVR–04/02Figure 46. Analog to Digital Converter Block SchematicOperation The ADC converts an analog input voltage to a 10-bit dig

79ATtiny26(L)1477B–AVR–04/02minal, otherwise the gain stage will saturate at 0V (GND). This amplified value thenbecomes the analog input to the ADC. I

8ATtiny26(L) 1477B–AVR–04/02All of the register operating instructions in the instruction set have direct and single cycleaccess to all registers. The

80ATtiny26(L) 1477B–AVR–04/02The successive approximation circuitry requires an input clock frequency between50 kHz and 200 kHz. The ADC module contai

81ATtiny26(L)1477B–AVR–04/02Figure 49. ADC Timing Diagram, Single ConversionFigure 50. ADC Timing Diagram, Free Running ConversionTable 34. ADC Con

82ATtiny26(L) 1477B–AVR–04/02ADC Noise Canceler FunctionThe ADC features a noise canceler that enables conversion during ADC Noise Reduc-tion mode (se

83ATtiny26(L)1477B–AVR–04/02Figure 51. Differential Measurement RangeExample: ADMUX = 0xEB (ADC0 - ADC1, 20x gain, 2.56V reference, left adjusted res

84ATtiny26(L) 1477B–AVR–04/02ADC Multiplexer Selection Register – ADMUX• Bit 7, 6 – REFS1, REFS0: Reference Selection BitsThese bits select the voltag

85ATtiny26(L)1477B–AVR–04/02Note: 1. For offset measurements only. See “Offset Compensation Schemes” on page 87.Table 37. Input Channel and Gain Sele

86ATtiny26(L) 1477B–AVR–04/02ADC Control and Status Register – ADCSR• Bit 7 – ADEN: ADC EnableWriting a logical “1” to this bit enables the ADC. By cl

87ATtiny26(L)1477B–AVR–04/02• Bits 2..0 – ADPS2..0: ADC Prescaler Select BitsThese bits determine the division factor between the CK frequency and the

88ATtiny26(L) 1477B–AVR–04/02Scanning Multiple ChannelsSince change of analog channel always is delayed until a conversion is finished, theFree Runnin

89ATtiny26(L)1477B–AVR–04/02Figure 52. ADC Power ConnectionsPA0 (ADC0)(ADC10/RESET) PB7(ADC9/INT0/T0) PB6(ADC8/XTAL2) PB5(ADC7/XTAL1) PB4VCCPA1 (ADC1

9ATtiny26(L)1477B–AVR–04/02In-System Programmable Flash Program Memory The ATtiny26/L contains 2K bytes On-chip In-System Programmable Flash memory fo

90ATtiny26(L) 1477B–AVR–04/02I/O PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This

91ATtiny26(L)1477B–AVR–04/02Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 54 shows afunct

92ATtiny26(L) 1477B–AVR–04/02difference between a strong high driver and a pull-up. If this is not the case, the PUD bitin the MCUCR Register can be s

93ATtiny26(L)1477B–AVR–04/02signal transition on the pin will be delayed between ½ and 1½ system clock perioddepending upon the time of assertion.When

94ATtiny26(L) 1477B–AVR–04/02The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as

95ATtiny26(L)1477B–AVR–04/02Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure57 shows

96ATtiny26(L) 1477B–AVR–04/02The following subsections shortly describes the alternate functions for each port, andrelates the overriding signals to t

97ATtiny26(L)1477B–AVR–04/02Alternate Functions of Port A Port A has an alternate functions as analog inputs for the ADC and Analog Comparatorand pin

98ATtiny26(L) 1477B–AVR–04/02• ADC4, ADC3 Port – A, Bit 5, 4ADC4/ADC3: ADC Input Channel 4 and 3. Configure the port pins as inputs with theinternal p

99ATtiny26(L)1477B–AVR–04/02 Notes: 1. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag isenabled, the PCIE1 flag in G