Rainbow-electronics ATtiny28L Uživatelský manuál

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 90 Powerful Instructions – Most Single Clock C

10ATtiny28L/V1062E–10/01Subroutine and Interrupt Hardware StackThe ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. Thehard

11ATtiny28L/V1062E–10/01I/O Memory The I/O space definition of the ATtiny28 is shown in Table 2.Note: Reserved and unused locations are not shown in t

12ATtiny28L/V1062E–10/01an interrupt has occurred, and is set by the RETI instruction to enable subsequentinterrupts.• Bit 6 – T: Bit Copy StorageThe

13ATtiny28L/V1062E–10/01The most typical and general program setup for the Reset and Interrupt vectoraddresses are:Address Labels Code Comments$000 rj

14ATtiny28L/V1062E–10/01Figure 15. Reset Logic Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).Table

15ATtiny28L/V1062E–10/01Note: 1. Due to limited number of clock cycles in the start-up period, it is recommended thatceramic resonator be used.This ta

16ATtiny28L/V1062E–10/01Figure 16. MCU Start-up, RESET Tied to VCC.Figure 17. MCU Start-up, RESET Controlled ExternallyExternal Reset An external re

17ATtiny28L/V1062E–10/01Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-tion. On the falling edg

18ATtiny28L/V1062E–10/01• Bit 1 – EXTRF: External Reset FlagThis bit is set if an external reset occurs. The bit is cleared by a Power-on Reset, or by

19ATtiny28L/V1062E–10/01Interrupt Control Register – ICR• Bit 7 – INT1: External Interrupt Request 1 EnableWhen the INT1 bit is set (one) and I-bit in

2ATtiny28L/V1062E–10/01Description The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-tecture. By executing powerful i

20ATtiny28L/V1062E–10/01Note: When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its InterruptEnable bit. Otherwise, an interrupt c

21ATtiny28L/V1062E–10/01cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configuredas level interrupt.• Bit 5 – Res: R

22ATtiny28L/V1062E–10/01Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-down mode. In this mode, the

23ATtiny28L/V1062E–10/01Timer/Counter0 The ATtiny28 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0.Timer/Counter0 has prescaling se

24ATtiny28L/V1062E–10/01The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an externalpin. In addition, it can be stopped as de

25ATtiny28L/V1062E–10/01The Stop condition provides a Timer Enable/Disable function. The CK down dividedmodes are scaled directly from the CK oscillat

26ATtiny28L/V1062E–10/01Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling theWatchdog Timer prescaler, t

27ATtiny28L/V1062E–10/01• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer p

28ATtiny28L/V1062E–10/01Calibrated Internal RC OscillatorThe calibrated internal oscillator provides a fixed 1.2 MHz (nominal) clock at 3V and25°C. Th

29ATtiny28L/V1062E–10/01Hardware Modulator ATtiny28 features a built-in hardware modulator connected to a high-current output pad,PA2. The hardware mo

3ATtiny28L/V1062E–10/01rupt on low-level input feature enables the ATtiny28 to be highly responsive to externalevents, still featuring the lowest powe

30ATtiny28L/V1062E–10/01PA2 is the built-in, high-current LED driver and it is always an output pin. The outputbuffer can sink 25 mA at VCC = 2.0V. Wh

31ATtiny28L/V1062E–10/01Figure 23. The Hardware ModulatorFigure 24 to Figure 27 show examples on output from the Modulator. Figure 24 alsoshows the t

32ATtiny28L/V1062E–10/01Figure 26. Modulation with ONTIM = 1, MCONF = 011Note: Clock frequency: 3.64 MHz; modulation frequency: 455 kHz; duty-cycle:

33ATtiny28L/V1062E–10/012.4576 MHz 455 kHz 10.0 33% 1 0102.4576 MHz 455 kHz 10.0 50% 2 0013.2768 MHz 455 kHz 10.0 25% 1 0113.2768 MHz 455 kHz 10.0 50%

34ATtiny28L/V1062E–10/01Analog Comparator The analog comparator compares the input values on the positive input PB0 (AIN0) andnegative input PB1 (AIN1

35ATtiny28L/V1062E–10/01• Bit 2 – RES: Reserved BitThis bit is a reserved bit in the ATtiny28 and will always read as zero.• Bits 1, 0 - ACIS1, ACIS0:

36ATtiny28L/V1062E–10/01I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that the d

37ATtiny28L/V1062E–10/01Port A as General Digital I/O PA3, PA1 and PA0 are general I/O pins. The DDAn (n: 3,1,0) bits in PACR select thedirection of t

38ATtiny28L/V1062E–10/01Port A Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the figures.

39ATtiny28L/V1062E–10/01Port B Port B is an 8-bit input port.One I/O address location is allocated for the Port B Input Pins – PINB, $16. The Port BIn

4ATtiny28L/V1062E–10/01Clock Options The device has the following clock source options, selectable by Flash Fuse bits asshown in Table 1.Note: “1” mea

40ATtiny28L/V1062E–10/01• T0 – Port B, Bit 2T0, Timer/Counter0 Counter source. See the timer description for further details. If T0 isused as the coun

41ATtiny28L/V1062E–10/01Figure 32. Port B Schematic Diagram (Pin PB2)Figure 33. PORT B Schematic Diagram (Pins PB3 and PB4)DATA BUSMOSPULL-UPPB2RP:

42ATtiny28L/V1062E–10/01Figure 34. PORT B Schematic Diagram (Pins PB7 - PB5)Port D Port D is an 8-bit bi-directional I/O port with internal pull-up r

43ATtiny28L/V1062E–10/01Port D as General Digital I/O All eight pins in Port D have equal functionality when used as digital I/O pins.PDn, general I/O

44ATtiny28L/V1062E–10/01Memory ProgrammingProgram Memory Lock BitsThe ATtiny28 MCU provides two Lock bits that can be left unprogrammed (“1”) or can b

45ATtiny28L/V1062E–10/01Parallel Programming This section describes how to parallel program and verify Flash program memory, Lockbits and Fuse bits in

46ATtiny28L/V1062E–10/01.Enter Programming Mode The following algorithm puts the device in parallel programming mode:1. Apply 4.5 - 5.5V between VCC a

47ATtiny28L/V1062E–10/01Chip Erase The Chip Erase command will erase the Flash memory and the Lock bits. The Lock bitsare not reset until the Flash ha

48ATtiny28L/V1062E–10/011. Set BS to “1”. This selects high data.2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes l

49ATtiny28L/V1062E–10/01Reading the Fuse and Lock BitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to “Programmingthe Flash”

5ATtiny28L/V1062E–10/01External Clock To drive the device from an external clock source, XTAL2 should be left unconnectedwhile XTAL1 is driven as show

50ATtiny28L/V1062E–10/01Figure 38. Programming the Flash Waveforms (Continued)DATA HIGHDATAXA1XA0BSXTAL1WRRDY/BSYRESET+12VOE

51ATtiny28L/V1062E–10/01Parallel Programming CharacteristicsFigure 39. Parallel Programming TimingParallel Programming CharacteristicsTA = 25°C ± 10%

52ATtiny28L/V1062E–10/01Electrical CharacteristicsAbsolute Maximum RatingsOperating Temperature... -40°C to +85/105°C*NOTICE

53ATtiny28L/V1062E–10/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where th

54ATtiny28L/V1062E–10/01External Clock Drive WaveformsFigure 40. External Clock:Note: R should be in the range 3 - 100 kΩ, and C should be at least 2

55ATtiny28L/V1062E–10/01Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. All cur

56ATtiny28L/V1062E–10/01Figure 42. Active Supply Current vs. VCCFigure 43. Active Supply Current vs. VCC, Device Clocked by Internal OscillatorACTIV

57ATtiny28L/V1062E–10/01Figure 44. Active Supply Current vs. VCC, Device Clocked by External 32 kHz CrystalFigure 45. Idle Supply Current vs. Freque

58ATtiny28L/V1062E–10/01Figure 46. Idle Supply Current vs. VCCFigure 47. Idle Supply Current vs. VCC, Device Clocked by Internal OscillatorIDLE SUPP

59ATtiny28L/V1062E–10/01Figure 48. Idle Supply Current vs. VCC, Device Clocked by External 32 kHz CrystalFigure 49. Power-down Supply Current vs. VC

6ATtiny28L/V1062E–10/01Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a singl

60ATtiny28L/V1062E–10/01Figure 50. Power-down Supply Current vs. VCCAnalog comparator offset voltage is measured as absolute offset.Figure 51. Analo

61ATtiny28L/V1062E–10/01Figure 52. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V)Figure 53. Analog Comparator Input Leakage C

62ATtiny28L/V1062E–10/01Figure 54. Calibrated Internal RC Oscillator Frequency vs. VCCFigure 55. Watchdog Oscillator Frequency vs. VCCCALIBRATED RC

63ATtiny28L/V1062E–10/01Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 56. Pull-up Resistor Current vs. Input Vol

64ATtiny28L/V1062E–10/01Figure 58. I/O Pin Sink Current vs. Output Voltage. All pins except PA2 (VCC = 5V)Figure 59. I/O Pin Source Current vs. Outp

65ATtiny28L/V1062E–10/01Figure 60. I/O Pin Sink Current vs. Output Voltage, All Pins Except PA2 (VCC = 2.7V)Figure 61. I/O Pin Source Current vs. Ou

66ATtiny28L/V1062E–10/01Figure 62. PA2 I/O Pin Sink Current vs. Output Voltage (High Current Pin PA2; TA =25°C)Figure 63. I/O Pin Input Threshold Vo

67ATtiny28L/V1062E–10/01Figure 64. I/O Pin Input Hysteresis vs. VCC (TA = 25°C)00.020.040.060.080.10.120.140.160.182.7 4.0 5.0Input Hysteresis (V)VCC

68ATtiny28L/V1062E–10/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addr

69ATtiny28L/V1062E–10/01 Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

7ATtiny28L/V1062E–10/01rate interrupt vector in the interrupt vector table at the beginning of theprogram memory. The different interrupts have priori

70ATtiny28L/V1062E–10/01DATA TRANSFER INSTRUCTIONSLD Rd, Z Load Register Indirect Rd ← (Z) None 2ST Z, Rr Store Register Indirect (Z) ← Rr None 2MOV R

71ATtiny28L/V1062E–10/01Ordering InformationSpeed (MHz) Power Supply (Volts) Ordering Code Package Operation Range4 2.7 - 5.5 ATtiny28L-4ACATtiny28L-4

72ATtiny28L/V1062E–10/01Packaging Information32A8.75 (0.344) 8.75 (0.344)0.45 (0.018)0.30 (0.012)PIN 1 ID0.80 (0.0315) BSC 6.90 (0.272)0.20 (0.008)0.0

73ATtiny28L/V1062E–10/0128P334.80(1.370)34.54(1.360)8.26(0.325)7.62(0.300)10.20(0.400)MAX0.38(0.015)2.54(0.100)BSC3.56(0.140)3.05(0.120)4.57(0.180)MAX

74ATtiny28L/V1062E–10/0132M1-APIN 1 ID 2325 Orchard Parkway San Jose, CA 95131TITLE32M1-ARDRAWING NO. REV R32M1-A, 32-pad, 5x5x1.0mm body

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

8ATtiny28L/V1062E–10/01Register Direct, Single Register RdFigure 7. Direct Single Register AddressingThe operand is contained in register d (Rd).Regi

9ATtiny28L/V1062E–10/01I/O Direct Figure 10. I/O Direct AddressingOperand address is contained in six bits of the instruction word. n is the destinat