Rainbow-electronics DS1957 Uživatelský manuál

1 of 25 052300SECURITY FEATURES• Single-chip, physically secure coprocessorfor non-secure host• Arithmetic accelerator executes 1024-bitpublic key c

DS195710 of 25DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d)E1HREAD STATUS?NBUS MASTER RXNUMBER OF FREE BYTESIN INPUT BUFFERY1)FROM D

DS195711 of 25When reading data from the IPR that has not been processed by the microcomputer inside the DS1957,the bus master already knows the actua

DS195712 of 25START PROGRAM [77H]The DS1957 Crypto iButton includes a microcomputer that performs logical and mathematical functionson data it receive

DS195713 of 25READ STATUS [E1H]In addition to the Intermediate Product Register (IPR) and the I/O buffer for data exchange and exchangemanagement resp

DS195714 of 25WRITE STATUS [D2H]The 1-Wire UART Status (OWUS) is the only status byte that can be written by the bus master. Itresembles the counterp

DS195715 of 25HARDWARE CONFIGURATION Figure 5TTL-EQUIVALENTPORT PINSVDDSTRONGPULL-UPDATA INDATA OUTVPUPBUS MASTER1.5k Ohms1-WIRE BUSTO DS1954GND1-WIRE

DS195716 of 25READ ROM [33H]This command allows the bus master to read the DS1957’s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. Thi

DS195717 of 25OVERDRIVE MATCH ROM [69H]The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at OverdriveSpeed, allows the bu

DS195718 of 25ROM FUNCTIONS FLOW CHART Figure 6NYYYDS1954 TXPRESENCPULSE33HREADCOMMAN?55HMATCHCOMMAN?F0HSEARCHCOMMAN?CCHSKIPCOMMAN?DS1954 TXFAMILYCODE

DS195719 of 25ROM FUNCTIONS FLOW CHART Figure 6 (cont’d)NYY3CHOVERDRIVESKIP?69HOVERDRIVEMATCH?BIT 0MATCH?BIT 1MATCH?BIT 63MATCH?NNNYMASTER TX BIT 63NO

DS19572 of 25ISSUING AND ACTIVATION INFORMATIONSee www.ibutton.comEXAMPLES OF ACCESSORIESDS1410E Parallel Port Button HolderDS1402D-DB8 iButton Dot Re

DS195720 of 25READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated in Figure 8. All time slots are initiated by themaste

DS195721 of 25WRITE-ZERO TIME SLOTVPULLUPVPULLUP MINVIH MINVIL MAX0VtSLOTtRECtLOW0DS1954SAMPLING WINDOW60 µs15 µs(OD: 2 µs) (OD: 6 µs)Regular Speed60

DS195722 of 25which is sufficient to operate the 1-Wire interface and to maintain the STOP mode of the microcomputerand accelerator. Once the initial

DS195723 of 25CRC GENERATIONWith the DS1957 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an8-bit type and is stored i

DS195724 of 25PHYSICAL SPECIFICATIONSSize See mechanical drawingWeight 3.3 gramsHumidity 90% RH at 50°CAltitude 10,000 feetExpected Service Life 5 yea

DS195725 of 25AC ELECTRICAL CHARACTERISTICSOVERDRIVE SPEED (VPUP=4.0V to 5.5V; -20°C to +70°C)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESTime Slot tSLO

DS19573 of 2564-BIT LASERED ROMEach DS1957 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire familycode. The next 4

DS19574 of 25DS1957 FUNCTIONAL BLOCK DIAGRAM Figure 11-WIRE FUNCTIONCONTROL64-BIT LASEREDROM128-BYTEINTERMEDIATEPRODUCTREGISTERDATA TRANSFERAND CONTR

DS19575 of 25HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 264-BIT LASERED ROM Figure 3DATA TRANSFER AND CONTROL FUNCTION COMMANDSThe “Data Trans

DS19576 of 25WRITE INTERMEDIATE PRODUCT REGISTER (IPR) [0FH]The intermediate product register is used to transfer firmware command codes and data to t

DS19577 of 25DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4MASTER TX DATA TRANSFER ORCONTROL FUNCTION COMMAND0FHWRITE IPR?AAHREAD IPR?NBUS MAS

DS19578 of 25DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d)2DHWRITE I/OBUFFER?NBUS MASTER TXLENGTH BYTEBUS MASTER TXDATA BYTELAST BYT

DS19579 of 25DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d)77HSTART PROGRAM?NBUS MASTER TX 6D43HRELEASE SEQUENCECOMMANDUNDERSTOOD?BUS