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HT49R70A-1
8-Bit LCD Type OTP MCU
Rev. 1.00 1 December 4, 2001
Features
·
Operating voltage: 3.0V~5.5V
·
8 input lines
·
16 bidirectional I/O lines
·
Two external interrupt input
·
One 8-bit and one 16-bit programmable timer/event
counter with PFD (programmable frequency divider)
function
·
LCD driver with 41´3or40´4 segments
·
8K´16 program memory EPROM
·
224´8 data memory RAM
·
Real Time Clock (RTC)
·
8-bit prescaler for RTC
·
Watchdog Timer
·
Buzzer output
·
On-chip crystal, RC and 32768Hz crystal oscillator
·
HALT function and wake-up feature reduce power
consumption
·
8-level subroutine nesting
·
Bit manipulation instruction
·
16-bit table read instruction
·
Up to 0.5ms instruction cycle with 8MHz system clock
·
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
100-pin QFP package
General Description
The HT49R70A-1 is an 8-bit high performance single
chip MCU. Its single cycle instruction and two-stage
pipeline architecture make it suitable for high speed ap
-
plications. The device is also suitable for use in multiple
LCD low power applications such as scales, leisure
products, high-level household appliances, hand held
LCD products, and battery operated systems in particu
-
lar.
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Shrnutí obsahu

Strany 1 - 8-Bit LCD Type OTP MCU

HT49R70A-18-Bit LCD Type OTP MCURev. 1.00 1 December 4, 2001Features·Operating voltage: 3.0V~5.5V·8 input lines·16 bidirectional I/O lines·Two externa

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HT49R70A-1Rev. 1.00 10 December 4, 2001Accumulator - ACCThe accumulator (ACC) is related to the ALU opera-tions. It is also mapped to location 05H of

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HT49R70A-1Rev. 1.00 11 December 4, 2001gram which corrupts the desired control sequence, thecontents should be saved in advance.External interrupts ar

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HT49R70A-1Rev. 1.00 12 December 4, 2001The Timer/Event Counter 0 interrupt request flag (T0F),external interrupt 1 request flag (EIF1), external inter

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HT49R70A-1Rev. 1.00 13 December 4, 2001The WDT time-out period is fixed as fS/216.If the WDT clock source chooses the internal WDT oscil-lator, the ti

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HT49R70A-1Rev. 1.00 14 December 4, 2001Real time clock - RTCThe real time clock (RTC) is operated in the same man-ner as the time base that is used to

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HT49R70A-1Rev. 1.00 15 December 4, 2001The WDT time-out during HALT differs from other chipreset conditions, for it can perform a ²warm reset² thatres

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HT49R70A-1Rev. 1.00 16 December 4, 2001The register states are summarized below:Register Reset (Power On)WDT Time-out(Norma Operation)RESReset(Normal

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HT49R70A-1Rev. 1.00 17 December 4, 2001In the event count or timer mode, the timer/event coun-ter starts counting at the current contents in thetimer/

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HT49R70A-1Rev. 1.00 18 December 4, 2001T ES y s t e m C l o c kT N 1T N 0T M R 1T N 1T N 0T O NP u l s e W i d t hM e a s u r e m e n tM o d e C

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HT49R70A-1Rev. 1.00 19 December 4, 2001Input/output portsThere are two 8-bit bidirectional input/output ports, PAand PC and one 8-bit input port PB. P

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Block DiagramHT49R70A-1Rev. 1.00 2 December 4, 2001P r o g r a mC o u n t e rP r o g r a mE P R O MI n s t r u c t i o nR e g i s t e rI n s t r u c t

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HT49R70A-1Rev. 1.00 20 December 4, 2001LCD display memoryThe HT49R70A-1 provides an area of embedded datamemory for LCD display. This area is located

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HT49R70A-1Rev. 1.00 21 December 4, 2001LCD driver outputThe output number of the HT49R70A-1 LCD driver canbe 41´2or41´3or40´4 by option (i.e., 1/2duty

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HT49R70A-1Rev. 1.00 22 December 4, 2001C O M 0 C O M 1 C O M 2 C O M 3 L C D s e g m e n t s O NC O M 2 s i d e l i g h t e dV A V BV CV

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HT49R70A-1Rev. 1.00 23 December 4, 2001Low voltage reset/detector functionsThere is a low voltage detector (LVD) and a low voltage reset circuit (LVR)

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HT49R70A-1Rev. 1.00 24 December 4, 2001OptionsPull-high selection. This option is to decide whether the pull-high resistance is visible or not on the

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Application CircuitsHT49R70A-1Rev. 1.00 25 December 4, 2001O S C 1O S C 2P A 0 ~ P A 7P B 0 ~ P B 7fS Y S/ 4R C o s c i l l a t o r a p p l i c a

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Instruction Set SummaryMnemonic DescriptionFlagAffectedArithmeticADD A,[m]ADDM A,[m]ADD A,xADC A,[m]ADCM A,[m]SUB A,xSUB A,[m]SUBM A,[m]SBC A,[m]SBCM

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Mnemonic DescriptionFlagAffectedBranchJMP addrSZ [m]SZA [m]SZ [m].iSNZ [m].iSIZ [m]SDZ [m]SIZA [m]SDZA [m]CALL addrRETRET A,xRETIJump unconditionallyS

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Instruction DefinitionADC A,[m] Add data memory and carry to the accumulatorDescription The contents of the specified data memory, accumulator and the

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AND A,[m] Logical AND accumulator with data memoryDescription Data in the accumulator and the specified data memory perform a bitwise logical_AND op-e

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Pin AssignmentHT49R70A-1Rev. 1.00 3 December 4, 2001H T 4 9 R 7 0 A - 1 1 0 0 Q F P - A1234567891 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42

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CLR [m].i Clear bit of data memoryDescription The bit i of the specified data memory is cleared to 0.Operation[m].i ¬ 0Affected flag(s)TC2 TC1 TO PD O

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CPLA [m] Complement data memory and place result in the accumulatorDescriptionEach bit of the specified data memory is logically complemented (1¢s com

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HALT Enter power down modeDescription This instruction stops program execution and turns off the system clock. The contents ofthe RAM and registers ar

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MOV A,x Move immediate data to the accumulatorDescription The 8-bit data specified by the code is loaded into the accumulator.OperationACC ¬ xAffected

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RET Return from subroutineDescription The program counter is restored from the stack. This is a 2-cycle instruction.OperationPC ¬ StackAffected flag(s

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RLC [m] Rotate data memory left through carryDescription The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re

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RRCA [m] Rotate right through carry and place result in the accumulatorDescription Data of the specified data memory and the carry flag are rotated 1

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SET [m] Set data memoryDescription Each bit of the specified data memory is set to 1.Operation[m] ¬ FFHAffected flag(s)TC2 TC1 TO PD OV Z AC C¾¾¾¾¾¾¾¾

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SUB A,[m] Subtract data memory from the accumulatorDescription The specified data memory is subtracted from the contents of the accumulator, leaving t

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SZ [m] Skip if data memory is 0Description If the contents of the specified data memory are 0, the following instruction, fetched duringthe current in

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Pin DescriptionPin Name I/O Options DescriptionPA0/BZPA1/BZPA2PA3/PFDPA4~PA7I/OWake-upPull-highor NoneCMOS orNMOSPA0~PA7 constitute an 8-bit bidirecti

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XOR A,[m] Logical XOR accumulator with data memoryDescription Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-si

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HT49R70A-1Rev. 1.00 41 December 4, 2001Copyright Ó 2001 by HOLTEK SEMICONDUCTOR INC.The information appearing in this Data Sheet is believed to be acc

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D.C. CharacteristicsTa=25°CSymbol ParameterTest ConditionsMin. Typ. Max. UnitVDDConditionsVDDOperating Voltage¾¾3.0¾5.5 VIDD1Operating Current (Crysta

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A.C. CharacteristicsTa=25°CSymbol ParameterTest ConditionsMin. Typ. Max. UnitVDDConditionsfSYS1System Clock (Crystal OSC)3V¾400¾4000 kHz5V¾400¾8000 kH

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HT49R70A-1Rev. 1.00 7 December 4, 2001Functional DescriptionExecution flowThe system clock is derived from either a crystal or anRC oscillator or a 32

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HT49R70A-1Rev. 1.00 8 December 4, 2001When a control transfer takes place, an additionaldummy cycle is required.Program memory - EPROMThe program memo

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HT49R70A-1Rev. 1.00 9 December 4, 2001Stack register - STACKThe stack register is a special part of the memory usedto save the contents of the PC. The

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