
19
T89C51CC01
Rev. D – 17-Dec-01
Figure 6. Mode Switching Waveforms
Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be
aware that all peripherals using the clock frequency as a time reference (UART, timers...)
will have their time reference divided by two. For example a free running timer generating
an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a
4800 baud rate will have a 9600 baud rate.
6.2 Register Table 12. CKCON Register
CKCON (S:8Fh)
Clock Control Register
XTAL2
XTAL1
CPU
X2 bit
X2STD STD
76543210
CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number
Bit
Mnemonic Description
7CANX2
CAN clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6WDX2
Watchdog clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5 PCAX2
Programmable Counter Array clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SIX2
Enhanced UART clock (MODE 0 and 2) (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer2 clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer1 clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
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