16
ATF1504ASV(L)
1409H–PLD–09/02
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlledbythe Test Access Port (TAP)controller
in the ATF1504ASV(L). The boundary-scan technique involvesthe inclusion of a shift-
registerstage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundariescanbe controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in orderto
support boundary-scan testing. The ATF1504ASV(L)doesnotcurrently include aTest
Reset(TRST) input pin because the TAP controller is automatically resetatpower-up.
The five JTAG modes supportedinclude:SAMPLE/PRELOAD, EXTEST, BYPASS,
IDCODEandHIGHZ. The ATF1504ASV(L)’sISP can be fully describedusingJTAG’s
BSDL as described in IEEE Standard 1149.1b. This allows ATF1504ASV(L)program-
ming to be described and implemented using any one of the third-party development
tools supporting this standard.
The ATF1504ASV(L) has the option of using four JTAG-standard I/O pins for boundary-
scan testing (BST) and in-system programming (ISP) purposes. The ATF1504ASV(L)is
programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The JTAG feature is a programmable
option. If JTAG (BST or ISP)isnotneeded, thenthe four JTAG control pins are avail-
able as I/Opins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1504ASV(L)containsupto68I/O pins and four input pins, dependingonthe
device type and package type selected. Each input pin and I/O pin has its own bound-
ary-scan cell (BSC) in order to support boundary-scan testing as describedindetail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chainedtogether through
the capture registers. Input to the capture register chain is fedinfromthe TDI pin while
the output is directedtothe TDOpin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generatedinternally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration
for Input and I/O Pins
(Except JTAG TAP
Pins)
Note:The AT F 1504ASV(L) has pull-up option on TMS and TDIpins. This feature is selectedas
adesign option.
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