Rainbow-electronics AT89C5122 Uživatelský manuál stáhnout pdf (Strana 51)

AT8xC5122/23

4202E–SCR–06/06

Reset Value = X0X0 X000b

Table 26. Clock Configuration Register 0 - CKCON0 (S:8Fh)

76543210

-WDX2- SIX2 - T1X2T0X2X2

Bit Number Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6WDX2

Watchdog clock

This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect.

Cleared to bypass the PR1 prescaler.

Set to select the PR1 output for this peripheral.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4SIX2

Enhanced UART clock (Mode 0 and 2)

This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect.

Cleared to bypass the PR1 prescaler.

Set to select the PR1 output for this peripheral.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2T1X2

Timer 1 clock

This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect.

Cleared to bypass the PR1 prescaler.

Set to select the PR1 output for this peripheral.

1T0X2

Timer 0 clock

This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect.

Cleared to bypass the PR1 prescaler.

Set to select the PR1 output for this peripheral.

0X2

System clock Control bit

Cleared to select the PR1 output for CPU and all the peripherals .

Set to bypass the PR1 prescaler and to enable the individual peripherals ‘X2’

bits.

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 212 213

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Rainbow-electronics AT89C5122 Uživatelský manuál Strana 51