Rainbow-electronics AT24C16A Uživatelský manuál

1Features• Write Protect Pin for Hardware Data Protection – Utilizes Different Array Protection Compared to the AT24C02/04/08/16• Low-voltage and Stan

10AT24C02A/04A/08A/16A0976D–12/01Read Operations Read operations are initiated the same way as write operations with the exception thatthe read/write

11AT24C02A/04A/08A/16A0976D–12/01Figure 2. Byte WriteFigure 3. Page WriteFigure 4. Current Address ReadSTARTMSBMSBLSBSTOPWRITESDA LINEDEVICEADDRESS

12AT24C02A/04A/08A/16A0976D–12/01Figure 5. Random ReadFigure 6. Sequential ReadSTARTSTARTMSBSTOPWRITEREADSDA LINEDEVICEADDRESSDUMMY WRITEWORDADDRESS

13AT24C02A/04A/08A/16A0976D–12/01AT24C02A Ordering InformationtWR (max)(ms)ICC (max)(µA)ISB (max)(µA)fMAX(kHz) Ordering Code Package Operation Range10

14AT24C02A/04A/08A/16A0976D–12/01AT24C04A Ordering InformationtWR (max)(ms)ICC (max)(µA)ISB (max)(µA)fMAX(kHz) Ordering Code Package Operation Range10

15AT24C02A/04A/08A/16A0976D–12/01AT24C08A Ordering InformationtWR (max)(ms)ICC (max)(µA)ISB (max)(µA)fMAX(kHz) Ordering Code Package Operation Range10

16AT24C02A/04A/08A/16A0976D–12/01AT24C16A Ordering InformationtWR (max)(ms)ICC (max)(µA)ISB (max)(µA)fMAX(kHz) Ordering Code Package Operation Range10

17AT24C02A/04A/08A/16A0976D–12/01Packaging Information8P3 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead (0.300&q

18AT24C02A/04A/08A/16A0976D–12/018S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lea

19AT24C02A/04A/08A/16A0976D–12/018T– TSSOP1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. 10/26/01COMMON DIMENSIONS(Unit

2AT24C02A/04A/08A/16A0976D–12/01Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM devi

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

3AT24C02A/04A/08A/16A0976D–12/01The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8Kdevices may be addressed on a single

4AT24C02A/04A/08A/16A0976D–12/01Note: 1. VIL min and VIH max are reference only and are not tested.DC CharacteristicsApplicable over recommended opera

5AT24C02A/04A/08A/16A0976D–12/01Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).2. This parameter is characterized and is

6AT24C02A/04A/08A/16A0976D–12/01Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the

7AT24C02A/04A/08A/16A0976D–12/01Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:

8AT24C02A/04A/08A/16A0976D–12/01Data ValidityStart and Stop DefinitionOutput Acknowledge

9AT24C02A/04A/08A/16A0976D–12/01Device Addressing The 2K, 4K and 8K EEPROM devices all require an 8 bit device address word followinga start condition