Rainbow-electronics BR24L16FVM-W Uživatelský manuál stáhnout pdf (Strana 6)

BR24L16-W / BR24L16F-W / BR24L16FJ-W /

Memory ICs

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Synchronous data timing

BUF

HIGH

HD :

STA t

LOW

SCL

START BIT STOP BIT

SCL

SDA

: DAT t

: DAT

: STOt

: STAt

: STA

SDA

(OUT)

SDA

(IN)

Fig.4 SYNCHRONOUS DATA TIMING

•

SDA data is latched into the chip at the rising edge of SCL clock.

•

Output data toggles at the falling edge of SCL clock.

Write cycle timing

ACKD0

SDA

SCL

START CONDITIONSTOP CONDITION

WRITE DATA (n)

Fig.5 WRITE CYCLE TIMING

1 2 3 4 5 6 7 8 9 10 11 ... 24 25

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Rainbow-electronics BR24L16FVM-W Uživatelský manuál Strana 6