Rainbow-electronics DS2165Q Uživatelský manuál

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2165/DS2165Q041295 10/17PCM AND ADPCM INPUT/OUTPUTSince the organization of the input and output time slotson the DS2165 does not depend on the algo

DS2165/DS2165Q041295 11/17TIME SLOT RESTRICTIONSUnder certain conditions, the DS2165 does containsome restrictions on the output time slots that are a

DS2165/DS2165Q041295 12/17ABSOLUTE MAXIMUM RATINGS*Voltage on any Pin Relative to Ground -1.0V to +7.0V Operating Temperature 0°C to 70°C Storage Temp

DS2165/DS2165Q041295 13/17PCM INTERFACE (0°C to 70°C; VDD=5V +10%)AC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% – 10% for DS2165QL)PARAMETER SYMBOL M

DS2165/DS2165Q041295 14/17SERIAL PORT (0°C to 70°C; VDD=5V + 10%)AC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% – 10% for DS2165QL)PARAMETER SYMBOL MI

DS2165/DS2165Q041295 15/17MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14MCLKRSTtRMtFMtRSTtPMtWMHtWMLSERIAL PORT AC TIMING DIAGRAM Figure 15SCLKSDICS

DS2165/DS2165Q041295 16/17DS2165 16/24/32KBPS ADPCM PROCESSOR 24–PIN DIPABCEFGHJKD1PKG 24-PINDIM MIN MAXA IN.MM1.15029.211.26032.00B IN.MM0.2506.350.2

CH1N1 E E1 D1 D D2 E2e1CA1A2 ABL1B1This drawing controlled by drawing number 56–G4001–001.DS2165/DS2165Q041295 17/17DS2165Q 16/24/32KBPS ADPCM PROCE

DS2165/DS2165Q041295 2/17OVERVIEWThe DS2165 contains three major functional blocks: ahigh performance (10 MIPS) DSP engine, two indepen-dent PCM inter

DS2165/DS2165Q041295 3/17PIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 RST I Reset. A high-low-high transition resets the algorithm. The device

DS2165/DS2165Q041295 4/17DS2165 BLOCK DIAGRAM Figure 1X SIDE PCM/ADPCMDATA INTERFACESERIAL PORT CONTROL/HARDWARE MODE LOGICY SIDE PCM/ADPCMDATA INTER

DS2165/DS2165Q041295 5/17ADDRESS/COMMAND BYTE Figure 3(MSB) (LSB)– X/Y A5 A4 A3 A2 A1 A0SYMBOL POSITION NAME AND DESCRIPTION– ACB.7 Reserved; must be

DS2165/DS2165Q041295 6/17INPUT TIME SLOT REGISTER Figure 5(MSB) (LSB)– – D5 D4 D3 D2 D1 D0SYMBOL POSITION NAME AND DESCRIPTION- ITR.7 Reserved; must

DS2165/DS2165Q041295 7/17DS2165 µ-LAW PCM INTERFACE Figure 7TIME SLOT 0 TIME SLOT N TIME SLOT 0TIME SLOT 31MSBLSBMSBLSBDON’T CARE3-STATEDON’T CARE3

DS2165/DS2165Q041295 8/17DS2165 A-LAW ADPCM INTERFACE Figure 10TIMESLOT 0TIMESLOT 1TIMESLOT NTIMESLOT 62TIMESLOT 63TIMESLOT 0CLKX, CLKYFSX, FSYXIN, Y

DS2165/DS2165Q041295 9/17ALGORITHM SELECT FOR HARDWARE MODE Table 4ALGORITHM CONFIGURATION OF A1 AND A464Kbps to/from 32Kbps Tie both A1 and A4 to VS