Rainbow-electronics DS2152 Uživatelský manuál

Copyright 1997 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2152031897 10/79and is used to clock data through the receive sideframer.Receive Positive Data Output [RPOSO]. Updated onthe rising edge of RCLKO w

DS2152031897 11/79RCLKI pins. Tie high to connect the the line interface cir-cuitry to the framer/formatter circuitry and deactivatethe TPOSI/TNEGI/T

DS2152031897 12/79ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W13 R/W Transmit Code Definition TCD14 R/W Receive Up Code Definition RUPCD15 R/W Receiv

DS2152031897 13/79ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W34 R/W Transmit Channel Blocking 3 TCBR335 R/W Transmit Control 1 TCR136 R/W Transmit C

DS2152031897 14/79ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W55 R/W Transmit Channel 6 TC656 R/W Transmit Channel 7 TC757 R/W Transmit Channel 8 TC8

DS2152031897 15/79ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W76 R/W Transmit Signaling 7 TS777 R/W Transmit Signaling 8 TS878 R/W Transmit Signaling

DS2152031897 16/793.0 CONTROL, ID AND TEST REGISTERThe operation of the DS2152 is configured via a set ofeleven control registers. Typically, the con

DS2152031897 17/79OOF2 RCR1.4 Out Of Frame Select 2.0 = follow RCR1.51 = 2/6 frame bits in errorSYNCC RCR1.3 Sync Criteria.In D4 Framing Mode0 = searc

DS2152031897 18/79MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select.0 = count errors in the framing bit position1 = count the number

DS2152031897 19/79TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)(MSB) (LSB)TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM TB7ZSSYMBOL POSITION NAME AND D

DS2152031897 2/79access and control the operation of the unit. Quickaccess via the parallel control port allows a single con-troller to handle many T

DS2152031897 20/79ODF CCR1.6 Output Data Format.0 = bipolar data at TPOSO and TNEGO1 = NRZ data at TPOSO; TNEGO = 0RSAO CCR1.5 Receive Signaling All O

DS2152031897 21/79CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)(MSB) (LSB)TFM TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDLSYMBOL POSITION NAME AND DESC

DS2152031897 22/79ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elas-tic stores to a known depth. Should be t

DS2152031897 23/79RPCSI CCR4.6 Receive Per–Channel Signaling Insert. See Section 7.2 for more details.0 = do not use RCHBLK to determine which channe

DS2152031897 24/79TCM4 CCR5.4 Transmit Channel Monitor Bit 4. MSB of a channel decode that deter-mines which transmit channel data will appear in the

DS2152031897 25/79– CCR7.6 Remote Loopback.0 = loopback disabled1 = loopback enabled– CCR7.5 Not Assigned. Should be set to zero when written to.– CC

DS2152031897 26/794.0 STATUS AND INFORMATIONREGISTERSThere is a set of nine registers that contain informationon the current real time status of the D

DS2152031897 27/7916ZD RIR1.5 Sixteen Zero Detect. Set when a string of at least sixteen consecutivezeros (regardless of the length of the string) ha

DS2152031897 28/79RL0 RIR3.6 Receive Level BIt 0. See Table 4–1.JALT RIR3.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reache

DS2152031897 29/79ALARM CRITERIA Table 4–2ALARM SET CRITERIA CLEAR CRITERIABlue Alarm (AIS)(see note 1 below)when over a 3 ms window,5 or less zeros

DS2152031897 3/79Reader’s NoteThis data sheet assumes a particular nomenclature ofthe T1 operating environment. In each 125 us frame,there are 24 eig

DS2152031897 30/79IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)(MSB) (LSB)LUP LDN LOTC SLIP RBL RYEL LRCL RLOSSYMBOL POSITION NAME AND DESCRIPTIONL

DS2152031897 31/79RFDL IMR2.4 Receive FDL Buffer Full.0 = interrupt masked1 = interrupt enabledTFDL IMR2.3 Transmit FDL Buffer Empty.0 = interrupt mas

DS2152031897 32/79LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5–1COUNT EXCESSIVEZEROS? (RCR1.7)B8ZS ENABLED?(CCR2.2)WHAT IS COUNTEDIN THE LCVCRsno

DS2152031897 33/79errors in the FPS framing pattern (in the ESF mode).When the MOSCR is operated in this mode, it is dis-abled during receive loss of

DS2152031897 34/79CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)[repeated here from section 3 for convenience](MSB) (LSB)TJC LLB LIAIS TCM4 TCM3 TCM

DS2152031897 35/79– CCR5.6 Not Assigned. Should be set to zero when written.– CCR5.5 Not Assigned. Should be set to zero when written .RCM4 CCR5.4 R

DS2152031897 36/797.0 SIGNALING OPERATIONThe DS2152 contains provisions for both processorbased (i.e., software based) signaling bit access and forhar

DS2152031897 37/79of a change in signaling by setting the IMR2.0 bit. Oncea signaling change has been detected, the user has atleast 2.75 ms to read

DS2152031897 38/79the lower nibble of each channel. Hence, bits 5 and 6contain the same data as bits 7 and 8 respectively ineach channel. The RSIG d

DS2152031897 39/79Each of the bit position in the Transmit Idle Registers(TIR1/TIR2/TIR3) represent a DS0 channel in the out-going frame. When these

DS2152031897 4/79DS2152 ENHANCED T1 SINGLE–CHIP TRANSCEIVER Figure 1–1 8 7434B8ZS DecoderBPV CounterSynchronizerAlarm DetectionLoop Code Detecto

DS2152031897 40/79TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address=40 to 4F and 50 to 57 Hex)(for brevity, only channel one is shown; see Table 1–3 fo

DS2152031897 41/79RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex) (MSB) (LSB)CH8CH7 CH6 CH5 CH4 CH3 CH2 CH1CH16 CH15 CH14 CH13 CH12 C

DS2152031897 42/799.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/RCBR2/RCBR3) and the Transmit ChannelBlocking Registers (TC

DS2152031897 43/7910.1 RECEIVE SIDEIf the receive side elastic store is enabled (CCR1.2=1),then the user must provide either a 1.544 MHz(CCR1.3=0) or

DS2152031897 44/79Performance Report Messages (PRM) as described inANSI T1.403 and the messages as described in AT&TTR54016. The HDLC controller

DS2152031897 45/79interrupts are present) when the user reads the event bitthat caused the interrupt to occur.11.1.3 Basic Operation DetailsTo allow t

DS2152031897 46/7911.1.4 HDLC/BOC Register DescriptionFDLC: FDL CONTROL REGISTER (Address=00 Hex)(MSB) (LSB)RBR RHR TFS THR TABT TEOM TZSD TCRCDSYMBOL

DS2152031897 47/79RPS FDLS.5 Receive Packet Start. Set when the HDLC controller detects an openingbyte. The setting of this bit prompts the user to

DS2152031897 48/79TNF FIMR.1 Transmit FIFO Not Full.0 = interrupt masked1 = interrupt enabledTMEND FIMR.0 Transmit Message End.0 = interrupt masked1 =

DS2152031897 49/79BOC5 RBOC.5 BOC Bit 5. Last bit received of the 6–bit codeword.BOC4 RBOC.4 BOC Bit 4.BOC3 RBOC.3 BOC Bit 3.BOC2 RBOC.2 BOC Bit 2.BO

DS2152031897 5/79PIN LIST Table 1–1PIN SYMBOL TYPE DESCRIPTION1 RCHBLK O Receive Channel Block2 NC – No Connect3 8MCLK O 8.192 MHz Clock4 NC – No Con

DS2152031897 50/79TFULL TPRM.1 Transmit FIFO Full. A real–time bit that is set high when the FIFO is full.UDR TPRM.0 Underrun. Set when the transmit

DS2152031897 51/7911.2 LEGACY FDL SUPP0RT11.2.1 OverviewIn order to provide backward compatibility to the olderDS2151 device, the DS2152 maintains the

DS2152031897 52/7911.2.3 Transmit SectionThe transmit section will shift out into the T1 datastream, either the FDL (in the ESF framing mode) or theFs

DS2152031897 53/79be selected via the IBCC register. The DS2152 willdetect repeating pattern codes in both framed andunframed circumstances with bit

DS2152031897 54/79C5 TCD.5 Transmit Code Definition Bit 5.C4 TCD.4 Transmit Code Definition Bit 4.C3 TCD.3 Transmit Code Definition Bit 3.C2 TCD.2 Tra

DS2152031897 55/79C4 RDNCD.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3 bit length isselected.C3 RDNCD.3 Receive Down Code Definiti

DS2152031897 56/79LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)(MSB) (LSB)L2 L1 L0 EGL JAS JABDS DJA TPDSYMBOL POSITION NAME AND DESCRIPTIONL

DS2152031897 57/79LINE BUILD OUT SELECT IN LICR Table 14.2L2 L1 L0 LINE BUILD OUT APPLICATION0 0 0 0 to 133 feet / 0dBDSX–1 / CSU0 0 1 133 to 266 feet

DS2152031897 58/79DS2152 EXTERNAL ANALOG CONNECTIONS Figure 14–11:11.15:1 (Rt = 0 Ohms) or1.36:1 (Rt = 4.7 Ohms)(larger winding toward0.47 uF(non–pola

DS2152031897 59/79DS2152 JITTER TOLERANCE Figure 14–2MINIMUM TOLERANCELEVEL AS PERTR 62411 (DEC. 90)DS2152TOLERANCEUNIT INTERVALS (UIpp)1K1001010.1110

DS2152031897 6/79PIN DESCRIPTIONTYPESYMBOL35 TLINK I Transmit Link Data36 NC – No Connect37 TSYNC I/O Transmit Sync38 TPOSI I Transmit Positive Data I

DS2152031897 60/79DS2152 JITTER ATTENUATION Figure 14–4FREQUENCY (Hz)0 dB–20 dB–40 dB–60 dB1 10 100 1K 10KJITTER ATTENUATION (dB)100KCURVE ACURVE BDS2

DS2152031897 61/79RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) Figure 15–2FRAME#1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

DS2152031897 62/79RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15–4RSYSCLKCHANNEL 24 CHANNEL 1CHANNEL 23LSB MSB RSERRS

DS2152031897 63/79TRANSMIT SIDE D4 TIMING Figure 15–61FRAME#TSYNC1/TFSYNCTSYNC2TSYNC3TLCLKRCHBLK42345678910111212345NOTES:1. TSYNC in the frame mode (

DS2152031897 64/79TRANSMIT SIDE BOUNDARY TIMING Figure 15–8CHANNEL 2CHANNEL 1LSB TCLKTSERTSYNC1TSYNC2TSIGTCHCLKTCHBLK3TLCLKTLINK4DON’T CAREAMSB LS

DS2152031897 65/79TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING(WITH ELASTIC STOREENABLED) Figure 15–10TSYSCLKACHANNEL 1CHANNEL 31LSB MSBCHANNEL 32 TSE

DS2152031897 66/79DS2152 TRANSMIT DATA FLOW Figure 15–11KEY= REGISTER= DEVICE PIN= SELECTOR TSER/TDATATC1 TO TC24TCC1 TO TCC3IBCCTDR10PER–CHANNEL COD

DS2152031897 67/79ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature for DS2152L 0°C to 70°COperating

DS2152031897 68/79AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX=1) (0°C to 70°C; VDD=5V ± 5% for DS2152L;–40°C to +85°C; VDD=5V ± 5% for DS2152L

DS2152031897 69/79AC CHARACTERISTICS – RECEIVE SIDE (0°C to 70°C; VDD=5V ± 5% for DS2152L;–40°C to +85°C; VDD=5V ± 5% for DS2152LN)PARAMETER SYMBOL MI

DS2152031897 7/79PIN DESCRIPTIONTYPESYMBOL70 A4 I Address Bus Bit 471 A5 I Address Bus Bit 572 A6 I Address Bus Bit 673 A7/ALE I Address Bus Bit 7 / A

DS2152031897 70/79AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD=5V ± 5% for DS2152L;–40°C to +85°C; VDD=5V ± 5% for DS2152LN)PARAMETER SYMBOL M

DS2152031897 71/79AC CHARACTERISTICS – NON–MULTIPLEXED PARALLEL PORT (MUX=0 ) (0°C to 70°C; VDD=5V ± 5% for DS2152L;–40°C to +85°C; VDD=5V ± 5% for DS

DS2152031897 72/79INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 16–2ALEWRRDCSAD0-AD7PWASHtASDtASLtCHtAHLtASDtASEDPWEHPWELtDSWtDHWtCStCYCMOTOROLA BUS

DS2152031897 73/79RECEIVE SIDE AC TIMING Figure 16–4RCLKRSER/RDATA/RSIGRCHCLKRCHBLKRFSYNC/RMSYNCRSYNC1RLCLK2RLINKtD1tD2tD2tD2tD2tD1tD2NOTES:1. RSYNC i

DS2152031897 74/79RECEIVE SYSTEM SIDE AC TIMING Figure 16–5RSER/RSIGRCHCLKRCHBLKRSYNC1RSYNC2tSUtPWtD4tD4tD3RSYSCLKtRtFtSLtSHtSPtD4RMSYNCtD4NOTES:1. RS

DS2152031897 75/79TRANSMIT SIDE AC TIMING Figure 16–7tRtFtCPtCLtCHtSUtD2tHDtD2tD2tD2tPWtSUtHDtSUTCLKTSER/TSIG/TDATATCHCLKTCHBLKTSYNC1TSYNC2TLCLK5TLINK

DS2152031897 76/79TRANSMIT SYSTEM SIDE AC TIMING Figure 16–8tRtFtSPtSLtSHtSUtD3tHDtD3tPWtSUTSYSCLKTSERTCHCLKTCHBLKTSSYNCNOTES:1. TSER is only sampled

DS2152031897 77/79INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 16–10A0 TO A7D0 TO D7WRCSRDADDRESS VALIDDATA VALID0 ns min.0 ns min.75 ns max.0 ns min

DS2152031897 78/79MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 16–13A0 TO A7D0 TO D7R/WCSDSADDRESS VALID0 ns min.0 ns min. 0 ns min.75 ns min.10

DS2152031897 79/79DS2152 100–PIN LQFPPKG 100–PINDIM MIN MAXA – 1.60A1 0.05 –A2 1.35 1.45B 0.17 0.27C 0.09 0.20D 15.80 16.20D1 14.00 BSCE 15.80 16.20E1

DS2152031897 8/79DS2152 PIN DESCRIPTION Table 1–2TRANSMIT SIDE DIGITAL PINSTransmit Clock [TCLK]. A 1.544 MHz primary clock.Used to clock data throug

DS2152031897 9/79onto the T1 line. Can be internally connected to TNEGOby tying the LIUC pin high. TPOSI and TNEGI can betied together in NRZ applic