Rainbow-electronics ADC11DL066 Uživatelský manuál

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ADC11DL066
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference
General Description
The ADC11DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 11-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single
3.3V power supply, the ADC11DL066 achieves 10.3 effective
bits and consumes just 686 mW at 66 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADCs are available on separate 11-bit buses with an
output data format choice of offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC11DL066 can be con-
nected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua-
tion process.
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Outputs 2.4V to 3.3V compatible
n Power down mode
n On-chip reference
Key Specifications
n Resolution 11 Bits
n DNL
±
0.25 LSB (typ)
n SNR (f
IN
= 10 MHz) 64 dB (typ)
n SFDR (f
IN
= 10 MHz) 80 dB (typ)
n Data Latency 6 Clock Cycles
n Power Consumption
— Operating 686 mW (typ)
— Power Down 75 mW (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
Connection Diagram
20077301
20040326
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
March 2004
ADC11DL066 Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference
© 2004 National Semiconductor Corporation DS200773 www.national.com
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Shrnutí obsahu

Strany 1 - ADC11DL066

ADC11DL066Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/DConverter w/Internal ReferenceGeneral DescriptionThe ADC11DL066 is a dual, low power monoli

Strany 2 - Block Diagram

Timing Diagram20077309Output TimingTransfer Characteristic20077310FIGURE 1. Transfer CharacteristicADC11DL066www.national.com 10

Strany 3

Typical Performance Characteristics VA=VD= +3.3V, VDR= +2.5V, fCLK= 66 MHz, fIN=10MHzunless otherwise statedDNL DNL vs. fCLK20077318 20077319DNL vs. C

Strany 4

Typical Performance Characteristics VA=VD= +3.3V, VDR= +2.5V, fCLK= 66 MHz, fIN=10MHzunless otherwise stated (Continued)INL vs. fCLKINL vs. Clock Duty

Strany 5

Typical Performance Characteristics VA=VD= +3.3V, VDR= +2.5V, fCLK= 66 MHz, fIN=10MHzunless otherwise stated (Continued)SNR, SINAD, SFDR vs. VREFSNR,

Strany 6

Typical Performance Characteristics VA=VD= +3.3V, VDR= +2.5V, fCLK= 66 MHz, fIN=10MHzunless otherwise stated (Continued)Distortion vs. VREFDistortion

Strany 7 - AC Electrical Characteristics

Typical Performance Characteristics VA=VD= +3.3V, VDR= +2.5V, fCLK= 66 MHz, fIN=10MHzunless otherwise stated (Continued)SPECTRAL PLOT, FIN= 10 MHz SPE

Strany 8

Functional DescriptionOperating on a single +3.3V supply, the ADC11DL066 usesa pipeline architecture and has error correction circuitry tohelp ensure

Strany 9 - Specification Definitions

Applications Information (Continued)For single frequency sine waves the full scale error in LSBcan be described as approximatelyEFS=2048(1-sin(90˚ + d

Strany 10 - Transfer Characteristic

Applications Information (Continued)A single-ended to differential conversion circuit is shown inFigure 5. Table 3 gives resistor values for that circ

Strany 11

Applications Information (Continued)Be very careful when driving a high capacitance bus. Themore capacitance the output drivers must charge for eachco

Strany 12

Ordering InformationIndustrial (−40˚C ≤ TA≤ +85˚C) PackageADC11DL066CIVS 64 Pin TQFPBlock Diagram20077302ADC11DL066www.national.com 2

Strany 13

Applications Information (Continued)4.0 POWER SUPPLY CONSIDERATIONSThe power supply pins should be bypassed with a 10 µFcapacitor and with a 0.1 µF ce

Strany 14

Applications Information (Continued)Be especially careful with the layout of inductors. Mutualinductance can change the characteristics of the circuit

Strany 15

Applications Information (Continued)7.0 COMMON APPLICATION PITFALLSDriving the inputs (analog or digital) beyond the powersupply rails. For proper ope

Strany 16 - Applications Information

Physical Dimensions inches (millimeters)unless otherwise noted64-Lead TQFP PackageOrdering Number ADC11DL066CIVSNS Package Number VEC64ALIFE SUPPORT P

Strany 17

Pin Descriptions and Equivalent CircuitsPin No. Symbol Equivalent Circuit DescriptionANALOG I/O152VINA+VINB+Differential analog Inputs. With a 1.0V re

Strany 18

Pin Descriptions and Equivalent Circuits (Continued)Pin No. Symbol Equivalent Circuit Description25–2934–39DA0–DA10Digital data output pins that make

Strany 19

Absolute Maximum Ratings (Notes 1,2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distri

Strany 20

Converter Electrical Characteristics (Continued)Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +

Strany 21

DC and Logic Electrical CharacteristicsUnless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR

Strany 22

AC Electrical Characteristics (Continued)Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, V

Strany 23 - NS Package Number VEC64A

Specification DefinitionsAPERTURE DELAY is the time after the rising edge of theclock to when the input signal is acquired or held for conver-sion.APE

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