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ADC12L063
12-Bit, 62 MSPS, 354 mW A/D Converter with Internal
Sample-and-Hold
General Description
The ADC12L063 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 62 Megasamples per second (MSPS), mini-
mum. This converter uses a differential, pipelined architec-
ture with digital error correction and an on-chip sample-and-
hold circuit to minimize die size and power consumption
while providing excellent dynamic performance. Operating
on a single 3.3V power supply, this device consumes just
354 mW at 62 MSPS, including the reference current. The
Power Down feature reduces power consumption to just 50
mW.
The differential inputs provide a full scale input swing equal
to
±
V
REF
with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 62 MSPS(min)
n Bandwidth 170MHz
n DNL
±
0.5 LSB(typ)
n INL
±
1.0 LSB(typ)
n SNR 66 dB(typ)
n SFDR 78 dB(typ)
n Data Latency 6 Clock Cycles
n Supply Voltage +3.3V
±
300 mV
n Power Consumption, 62 MHz 354 mW(typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20026301
November 2002
ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold
© 2002 National Semiconductor Corporation DS200263 www.national.com
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Shrnutí obsahu

Strany 1 - Sample-and-Hold

ADC12L06312-Bit, 62 MSPS, 354 mW A/D Converter with InternalSample-and-HoldGeneral DescriptionThe ADC12L063 is a monolithic CMOS analog-to-digital con

Strany 2 - Block Diagram

Timing Diagram20026309Output TimingTransfer Characteristic20026310FIGURE 1. Transfer CharacteristicADC12L063www.national.com 10

Strany 3

Typical Performance Characteristics VA=VD=VDR= 3.3V, fCLK= 62MHz, fIN= 10 MHz unlessotherwise statedDNL vs. VADNL vs. Clock Duty Cycle2002635920026360

Strany 4

Typical Performance Characteristics VA=VD=VDR= 3.3V, fCLK= 62MHz, fIN= 10 MHz unlessotherwise stated (Continued)SNR vs. VASNR vs. fCLK20026364 2002636

Strany 5

Typical Performance Characteristics VA=VD=VDR= 3.3V, fCLK= 62MHz, fIN= 10 MHz unlessotherwise stated (Continued)THD vs. fCLKTHD vs. Clock Duty Cycle20

Strany 6

Typical Performance Characteristics VA=VD=VDR= 3.3V, fCLK= 62MHz, fIN= 10 MHz unlessotherwise stated (Continued)SINAD vs. Duty Cycle SINAD vs. VREF200

Strany 7 - AC Electrical Characteristics

Typical Performance Characteristics VA=VD=VDR= 3.3V, fCLK= 62MHz, fIN= 10 MHz unlessotherwise stated (Continued)SFDR vs. VREFSFDR vs. Temperature20026

Strany 8

Functional DescriptionOperating on a single +3.3V supply, the ADC12L063 uses apipelined architecture and has error correction circuitry tohelp ensure

Strany 9 - Specification Definitions

Applications Information (Continued)For differential operation, each analog input signal shouldhave a peak-to-peak voltage equal to the input referenc

Strany 10 - Transfer Characteristic

Applications Information (Continued)bypassing and careful attention to the ground plane willreduce this problem. Additionally, bus capacitance beyondt

Strany 11

Applications Information (Continued)20026314FIGURE 5. Differential Drive Circuit of Figure 420026315FIGURE 6. Driving the Signal Inputs with a Transfo

Strany 12

Ordering InformationIndustrial (−40˚C ≤ TA≤ +85˚C) PackageADC12L063CIVY 32 Pin LQFPADC12L063CIVYX 32 Pin LQFP Tape and ReelADC12L063EVAL Evaluation Bo

Strany 13

Applications Information (Continued)4.0 POWER SUPPLY CONSIDERATIONSThe power supply pins should be bypassed with a 10 µFcapacitor and with a 0.1 µF ce

Strany 14

Applications Information (Continued)which they are used. Inductors should not be placed side byside, even with just a small part of their bodies besid

Strany 15

Physical Dimensions inches (millimeters)unless otherwise noted32-Lead LQFP PackageOrdering Number ADC12L063CIVYNS Package Number VBE32ALIFE SUPPORT PO

Strany 16 - Applications Information

Pin Descriptions and Equivalent CircuitsPin No. Symbol Equivalent Circuit DescriptionANALOG I/O2VIN+Non-Inverting analog signal Input. With a 1.0V ref

Strany 17

Pin Descriptions and Equivalent Circuits (Continued)Pin No. Symbol Equivalent Circuit Description14–19,22–27D0–D11Digital data output pins that make u

Strany 18

Absolute Maximum Ratings (Notes 1,2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distri

Strany 19

DC and Logic Electrical CharacteristicsUnless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V,

Strany 20

DC and Logic Electrical Characteristics (Continued)Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD

Strany 21

AC Electrical Characteristics (Continued)20026307Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors ar

Strany 22 - 32-Lead LQFP Package

Specification DefinitionsAPERTURE DELAY is the time after the rising edge of theclock to when the input signal is acquired or held for conver-sion.APE

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