Rainbow-electronics atmega16p Uživatelský manuál

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Features
High-performance, Low-power AVR
®
8-bit Microcontroller
Advanced RISC Architecture
130 Powerful Instructions – Most Single-clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
16K Bytes of In-System Self-Programmable Flash
Endurance: 1,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
1K Byte Internal SRAM
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x in TQFP
Package Only
Byte-oriented 2-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
32 Programmable I/O Lines
40-pin PDIP and 44-lead TQFP
Operating Voltages
2.7 - 5.5V for ATmega16L
4.5 - 5.5V for ATmega16
Speed Grades
0 - 8 MHz for ATmega16L
–0 - 16 MHz for ATmega16
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16
ATmega16L
Preliminary
Summary
Rev. 2466BS–09/01
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ava ila ble on ou r we b site at www.a tmel.com.
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Shrnutí obsahu

Strany 1 - Features

1Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 130 Powerful Instructions – Most Single-clock Cycle Exe

Strany 2

10ATmega16(L)2466BS–09/01CLH Clear Half Carry Flag in SREG H ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific descr. f

Strany 3

11ATmega16(L)2466BS–09/01Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range8 2.7 - 5.5V ATmega16L-8ACATmega16L-8PC44A4

Strany 4

12ATmega16(L)2466BS–09/01Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.006)

Strany 5

13ATmega16(L)2466BS–09/0140P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1.65(0

Strany 6

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

Strany 7

2ATmega16(L)2466BS–09/01Pin Configurations Figure 1. Pinouts ATmega16(XCK/T0) PB0(T1) PB1(INT2/AIN0) PB2(OC0/AIN1) PB3(SS) PB4(MOSI) PB5(MISO)

Strany 8

3ATmega16(L)2466BS–09/01Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing power

Strany 9

4ATmega16(L)2466BS–09/01The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly conne

Strany 10 - ATmega16(L)

5ATmega16(L)2466BS–09/01Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port

Strany 11

6ATmega16(L)2466BS–09/01Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C 7$3E ($5E) SP

Strany 12

7ATmega16(L)2466BS–09/01Notes: 1. When the OCDEN fuse is unprogrammed, the OSCCAL register is always accessed on this address. Refer to the debuggersp

Strany 13

8ATmega16(L)2466BS–09/01Instruction Set Summary Mnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

Strany 14 - 2466BS–09/01/xM

9ATmega16(L)2466BS–09/01BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2BRID k Branch if Interrupt Disabled if ( I = 0

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