Rainbow-electronics ATmega32L Uživatelský manuál stáhnout pdf (Strana 124)

124

ATmega32(L)

2503C–AVR–10/02

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

compare match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 119 for more details.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Table 54.

Timer/Counter Register –

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT2) while

the counter is running, introduces a risk of missing a compare match between TCNT2

and the OCR2 Register.

Table 53. Compare Output Mode, Phase Correct PWM Mode

(1)

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

01Reserved

1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare

match when downcounting.

1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare

match when downcounting.

Table 54. Clock Select Bit Description

CS22 CS21 CS20 Description

0 0 0 No clock source (Timer/Counter stopped).

001

clk

T2S

/(No prescaling)

010clk

T2S

/8 (From prescaler)

011

clk

T2S

/32 (From prescaler)

100

clk

T2S

/64 (From prescaler)

101clk

T2S

/128 (From prescaler)

110clk

/256 (From prescaler)

111clk

/1024 (From prescaler)

Bit 76543210

TCNT2[7:0] TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

1 2 ... 119 120 121 122 123 124 125 126 127 128 129 ... 312 313

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