Rainbow-electronics MAX5890 Uživatelský manuál stáhnout pdf (Strana 4)

MAX5890

14-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, external reference V

REFIO

= +1.2V, output load 50Ω double-ter-

minated, transformer-coupled output, I

OUT

= 20mA, T

= -40°C to +85°C, unless otherwise noted. Specifications at T

≥ +25°C are

guaranteed by production testing. Specifications at T

< +25°C are guaranteed by design and characterization. Typical values are at

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

ANALOG OUTPUT TIMING (Figure 3)

Output Fall Time t

FALL

90% to 10% (Note 3) 0.4 ns

Output Rise Time t

RISE

10% to 90% (Note 3) 0.4 ns

Output Propagation Delay t

Reference to data latency (Note 3) 2.5 ns

Output Settling Time To 0.025% of the final value (Note 3) 11 ns

Glitch Impulse Measured differentially 1

pV•s

OUT

= 2mA 30

Output Noise N

OUT

= 20mA 30

pA/√Hz

TIMING CHARACTERISTICS

Input Data Rate 600

MWps

Data Latency 5.5

Clock

cycles

Data to Clock Setup Time t

SETUP

Referenced to rising edge of clock (Note 4) -1.2

Data to Clock Hold Time t

HOLD

Referenced to rising edge of clock (Note 4)

2ns

Clock Frequency f

CLK

CLKP, CLKN 600

MHz

Minimum Clock Pulse-Width High

CLKP, CLKN 0.6 ns

Minimum Clock Pulse-Width Low

CLKP, CLKN 0.6 ns

Turn-On Time t

SHDN

External reference, PD falling edge to

output settle within 1%

350

µs

CMOS LOGIC INPUT (PD)

Input Logic-High V

0.7 x

DD3.3

Input Logic-Low V

0.3 x

DD3.3

Input Current I

-10

±1.8 +10

µA

Input Capacitance C

3pF

LVDS INPUTS

Differential Input High

IHLVDS

+100

Differential Input Low

ILLVDS

-100

Common-Mode Voltage Range

ICMLVDS

1.125 1.375

Differential Input Resistance

IDLVDS

110

Ω

Common-Mode Input Resistance R

ICMLVDS

3.2 kΩ

Input Capacitance

INLVDS

3pF

DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)

Clock Common-Mode Voltage CLKP and CLKN are internally biased

CLK

/ 2

Minimum Differential Input

Voltage Swing

0.5

P-P

1 2 3 4 5 6 7 8 9 ... 14 15

DAC with LVDS Inputs 1

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