
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 411 - Revision B2
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED DATAIN4[10:8]
7 6 5 4 3 2 1 0
DATAIN3[7:0]
BITS DESCRIPTION
[31:11] RESERVED
-
[10:0]
DATAIN4
Port4 input data register
The DATAIN4 indicates the status of each GPIO52~GPIO59,
GPIO68 and GPIO69 pin regardless of its operation mode. The
reserved bits will be read as 0s
GPIO Port5 Configuration Register (GPIO_CFG5)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
GPIO_CFG5 0xFFF8_3050 R/W GPIO port5 configuration register 0x0000_0000
31 30 29 28 27 26 25 24
RESERVED PT5CFG14 PT5CFG13 PT5CFG12
23 22 21 20 19 18 17 16
PT5CFG11 PT5CFG10 PT5CFG9 PT5CFG8
15 14 13 12 11 10 9 8
PT5CFG7 PT5CFG6 PT5CFG5 PT5CFG4
7 6 5 4 3 2 1 0
PT5CFG3 PT5CFG2 PT5CFG1 PT5CFG0
*In the following pin definition, mark with shading is default function.
11 10 01
00
PT5CFG0
Name Type Name Type Name Type
Name Type
PORT5_0 RESERVED RESERVED TXD0 O GPIO5 I/O
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