
1Features• Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• Medium-voltage and Standard-voltage Operation– 5.0 (V
10AT25080/160/320/6403260D–SEEPR–9/03Timing DiagramsSynchronous Data Timing (for Mode 0) WREN Timing WRDI Timing SOVOHVOLHI-ZHI-ZtVVALID INSIVIHVIL
11AT25080/160/320/6403260D–SEEPR–9/03RDSR Timing WRSR Timing CSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA OUTMSBHIGH IMPEDANCE15HIGH IMPEDAN
12AT25080/160/320/6403260D–SEEPR–9/03READ Timing WRITE Timing HOLD Timing CSSCKSISO000111222333...44556677891015 14 1311 20 21 22 23 24 25 26 27 28
13AT25080/160/320/6403260D–SEEPR–9/03 AT25080 Ordering InformationOrdering Code Package Operation RangeAT25080-10PA-5.0CAT25080N-10SA-5.0C8P38S1Automo
14AT25080/160/320/6403260D–SEEPR–9/03AT25160 Ordering InformationOrdering Code Package Operation RangeAT25160-10PA-5.0CAT25160N-10SA-5.0C8P38S1Automot
15AT25080/160/320/6403260D–SEEPR–9/03AT25320 Ordering InformationOrdering Code Package Operation RangeAT25320-10PA-5.0CAT25320N-10SA-5.0C8P38S1Automot
16AT25080/160/320/6403260D–SEEPR–9/03AT25640 Ordering InformationOrdering Code Package Operation RangeAT25640-10PA-5.0CAT25640N-10SA-5.0C8P38S1Automot
17AT25080/160/320/6403260D–SEEPR–9/03Packaging Information8P3 – PDIP 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.300&
18AT25080/160/320/6403260D–SEEPR–9/038S1 – JEDEC SOIC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lead (0.15
Printed on recycled paper.3260D–SEEPR–9/03 xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly
2AT25080/160/320/6403260D–SEEPR–9/03 Block Diagram Absolute Maximum Ratings*Operating Temperature... -55°C to +125°C*N
3AT25080/160/320/6403260D–SEEPR–9/03Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested.DC Characteristics(1) Note: 1
4AT25080/160/320/6403260D–SEEPR–9/03Note: 1. This parameter is characterized and is not 100% tested. AC Characteristics Applicable over recommended op
5AT25080/160/320/6403260D–SEEPR–9/03Serial Interface DescriptionMASTER: The device that generates the serial clock.SLAVE: Because the Serial Clock pin
6AT25080/160/320/6403260D–SEEPR–9/03SPI Serial Interface
7AT25080/160/320/6403260D–SEEPR–9/03Functional DescriptionThe AT25080/160/320/640 is designed to interface directly with the synchronous serial periph
8AT25080/160/320/6403260D–SEEPR–9/03WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one offour levels of protection. The
9AT25080/160/320/6403260D–SEEPR–9/03READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output)pin requires the following sequenc
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