Rainbow-electronics DS2181A Uživatelský manuál

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Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS2181A
CEPT Primary Rate Transceiver
DS2181A
041995 1/32
FEATURES
Single–chip primary rate transceiver meets CCITT
standards G.704, G.706 and G.732
Supports new CRC4-based framing standards and
CAS and CCS signalling standards
Simple serial interface used for device configuration
and control in processor mode
Hardware mode requires no host processor;
intended for stand-alone applications
Comprehensive, on-chip alarm generation, alarm
detection, and error logging logic
Shares footprint with DS2180A T1 Transceiver
Companion to DS2175 T1/CEPT Elastic Store,
DS2186 Transmit Line Interface, DS2187 Receive
Line Interface, and DS2188 Jitter Attenuator
5V supply; low-power CMOS technology
DESCRIPTION
The DS2181A is designed for use in CEPT networks
and supports all logical requirements of CCITT Red
Book Recommendations G.704, G.706 and G.732. The
transmit side generates framing patterns and CRC4
codes, formats outgoing channel and signalling data,
and produces network alarm codes when enabled. The
receive side decodes the incoming data and esta-
blishes frame, CAS multiframe, and CRC4 multiframe
alignments. Once synchronized, the device extracts
channel, signalling, and alarm data.
A serial port allows access to 14 on-chip control and sta-
tus registers in the processor mode. In this mode, a host
processor controls features such as error logging, per-
channel code manipulation, and alteration of the receive
synchronizer algorithm.
PIN ASSIGNMENT
INT
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
22
23
24
40-Pin DIP (600 MIL)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
VDD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
RCLK
RAF
RDMA
RRA
44-PIN PLCC
RFSA
TCHCLK
TCLK
RMSA
TFSYNC
TMSYNC
VDD
RLOS
RFER
RBV
RCL
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
6543214443424140
RNEG
RPOS
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
SDI
SDO
CS
SCLK
SPS
VSS
RRA
RDMA
RCTO
RAF
RCLK
RCSA
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1 2 3 4 5 6 ... 31 32

Shrnutí obsahu

Strany 1 - CEPT Primary Rate Transceiver

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

Strany 2 - 041995 2/32

DS2181A041995 10/32RCR: RECEIVE CONTROL REGISTER Figure 6(MSB) (LSB)– – RSM CMSC CMRC FRC SYNCE RESYNCSYMBOL POSITION NAME AND DESCRIPTION– RCR.7 Res

Strany 3 - 041995 3/32

DS2181A041995 11/32CCS SIGNALLINGCCS (selected when TCR.5 = 1 and/or when RCR.1 = 1)utilizes all bit positions of timeslot 16 in every frame formessa

Strany 4 - 041995 4/32

DS2181A041995 12/32TSD INPUT TIMING (TCR.6 = 1; TCR.5 = 0) Table 6FRAME # TIMESLOT SIGNALLINGDATA SAMPLED AT TSD0 171 1,182 2,193 3,204 4,215 5,226

Strany 5 - REGISTER SUMMARY Table 5

DS2181A041995 13/32CAS OUTPUT FORMAT IN TIMESLOT 16 Figure 8Frame 01Frame 1 Frame 150000XYXXABCD fortimeslot 1ABCD fortimeslot 17ABCD fortimeslot 15

Strany 6 - transi

DS2181A041995 14/32TXR: TRANSMIT EXTRA REGISTER Figure 10(MSB) (LSB)– – – – XB1 TDMA XB2 XB3SYMBOL POSITION NAME AND DESCRIPTION– TXR.7 Reserved; mus

Strany 7 - 041995 7/32

DS2181A041995 15/32TRANSMIT TIMINGA low-high transition at TMSYNC once per multiframe(every 2 milliseconds) or at a multiple of the multiframerate es

Strany 8 - 041995 8/32

DS2181A041995 16/32TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13TIMESLOT 30TCLKTMSYNC1,TFSYNCTMO1TCHCLKTAF2TSERTPOS3TNEGTIMESLOT 31 TIMESLOT 0FRAME

Strany 9 - 041995 9/32

DS2181A041995 17/32TRANSMIT SIGNALLING TIMESLOT TIMING Figure 14TCLKTCHCLKTSTSTIMESLOT 15 TIMESLOT 16 TIMESLOT 17RECEIVE SIGNALLINGReceive signallin

Strany 10 - CAS SIGNALLING

DS2181A041995 18/32RECEIVE MULTIFRAME TIMING Figure 15DATA VALIDFOR TIMESLOT 1RCLKRCHCLKRSDAB DCFRAME 2TIMESLOT 1 TIMESLOT 18DATA VALIDFOR TIMESLOT

Strany 11 - 041995 11/32

DS2181A041995 19/32RECEIVE MULTIFRAME BOUNDARY TIMING Figure 17RNEG,RPOSLSB MSBLSB MSBLSB MSBTIMESLOT 0FRAME 0FRAME 15FRAME 0LSB MSBTIMESLOT 1RCLKMS

Strany 12 - TSD INPUT TIMING Figure 7

DS2181A041995 2/32The hardware mode is intended for preliminary systemprototyping and/or retrofitting into existing systems.This mode requires no hos

Strany 13 - 041995 13/32

DS2181A041995 20/32RSR: RECEIVE STATUS REGISTER Figure 18(MSB) (LSB)RRA RDMA RSA1 RUA1 FSERR MFSERR RLOS ECSSYMBOL POSITION NAME AND DESCRIPTIONRRA R

Strany 14 - TRANSMIT EXTRA DATA

DS2181A041995 21/32RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 19(MSB) (LSB)RRA RDMA RSA1 RUA1 FSERR MFSERR RLOS ECSSYMBOL POSITION NAME AND DESCRIP

Strany 15 - TRANSMIT TIMING

DS2181A041995 22/32BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 20(MSB) (LSB)BVD7 BVD6 BVD5 BVD4 BVD3 BVD2 BVD1 BVD0SYMBOL POSITION NAME AND DESCRIP

Strany 16 - 041995 16/32

RCLKRCHCLKRSTSRFER1DS2181A041995 23/32RRAThe remote alarm output transitions high when a remotealarm is detected. A high-low transition indicates the

Strany 17 - RECEIVE SIGNALLING Table 7

RCLKRCHCLKRFSYNCRAFRCSYNCRFER4DS2181A041995 24/32CRC4 SUB-MULTIFRAME 2 ERRORED Figure 25RCLKRCHCLKRFSYNCRAFRCSYNCRFER2FRAME ALIGNMENT WORD ERRORED

Strany 18 - RSD TIMING Figure 16

DS2181A041995 25/32NOTES FOR FIGURES 23 THROUGH 27:1. CAS multiframe alignment word received in error; RFER will transition high at first error occur

Strany 19 - 041995 19/32

DS2181A041995 26/32ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -1.0V to 7.0VOperating Temperature 0°C to +70°CStorage Temperature

Strany 20 - 041995 20/32

DS2181A041995 27/32SERIAL PORT WRITE AC TIMING DIAGRAM Figure 28tCWHtCCtCHtRtFtCLtCCHtCDHtDCSCLKCSSDINOTE:1. Shaded regions indicate “don’t care” st

Strany 21 - SERVICING

DS2181A041995 28/32AC ELECTRICAL CHARACTERISTICS1,2 SERIAL PORT (0°C to 70°C, VDD = 5V + 5%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESSDI to SCLK Setup

Strany 22 - 041995 22/32

DS2181A041995 29/32AC ELECTRICAL CHARACTERISTICS1,2 RECEIVE (0°C to 70°C, VDD = 5V + 5%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESPropagation Delay RCL

Strany 23 - 041995 23/32

DS2181A041995 3/32TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe Sync. Low-high transit

Strany 24 - 041995 24/32

RCL,RBV,RLOS,RDMA,RRA,RFERtWHtPtWLtFtRRCLKRSER, RSDRMSYNC,RFSYNC,RCSYNC,RAF,RSTS,RCHCLKRSTRPOS, RNEGtPRDtRSTtSRDtHRDtPRAtPRSDS2181A041995 30/32TRANSM

Strany 25 - HARDWARE MODE

DS2181A041995 31/32DS2181A CEPT TRANSCEIVER (600 MIL DIP) 40–PINBDACKG HJEF1NINCHESDIM MIN MAXA 2.050 2.075B 0.530 0.550C 0.140 0.160D 0.600 0.625E 0

Strany 26 - =5V + 10%)

DS2181A041995 32/32DS2181AQ CEPT TRANSCEIVER (PLCC)CA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE IND

Strany 27 - AC TIMING Figure 29

DS2181A041995 4/32RECEIVE PIN DESCRIPTION (40–PIN DIP ONLY) Table 2BPIN SYMBOL TYPE DESCRIPTION21 RRA O Receive Remote Alarm. Transitions high when

Strany 28 - 041995 28/32

DS2181A041995 5/32POWER AND TEST PIN DESCRIPTION (40–PIN DIP ONLY) Table 4PIN SYMBOL TYPE DESCRIPTION20 VSS– Signal Ground. 0.0 volts.32 TEST I Test

Strany 29 - 041995 29/32

DS2181A041995 6/32SERIAL PORT INTERFACEPins 14 through 18 of the DS2181A serve as a micropro-cessor/microcontroller-compatible serial port. Fourteeno

Strany 30 - 041995 30/32

DS2181A041995 7/32ACB: ADDRESS COMMAND BYTE Figure 2(MSB) (LSB)BM – – ADD3 ADD2 ADD1 ADD0 R/WSYMBOL POSITION NAME AND DESCRIPTIONBM ACB.7 Burst Mode

Strany 31 - 041995 31/32

DS2181A041995 8/32TCR: TRANSMIT CONTROL REGISTER Figure 4(MSB) (LSB)TUA1 TSS TSM INBS NBS XBS TSA1 ODMSYMBOL POSITION NAME AND DESCRIPTIONTUA1 TCR.7

Strany 32 - 041995 32/32

DS2181A041995 9/32CCR: COMMON CONTROL REGISTER Figure 5(MSB) (LSB)– TAFP THDE RHDE TCE RCE SAS LLBSYMBOL POSITION NAME AND DESCRIPTION– CCR.7 Reserve

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