Rainbow-electronics AT89C5132 Uživatelský manuál stáhnout pdf (Strana 14)

AT8xC5132

4173A–8051–08/02

Figure 9. PLL Filter Connection

PLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as clock generation

is enabled, the user must wait until the lock indicator is set to ensure the clock output is

stable. The PLL clock frequency will depend on the audio interface clock frequencies.

Figure 10. PLL Programming Flow

PFILT

PLL

Programming

Configure Dividers

N6:0 = xxxxxxb

R9:0 = xxxxxxxxxxb

Enable PLL

PLLRES = 0

PLLEN = 1

PLL Locked?

PLOCK = 1?

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Rainbow-electronics AT89C5132 Uživatelský manuál Strana 14