Rainbow-electronics ATmega128RFA1 Uživatelský manuál stáhnout pdf (Strana 242)

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8266A-MCU Wireless-12/09

ATmega128RFA1

17.9.6 OCR0B – Timer/Counter0 Output Compare Register B

Bit 7 6 5 4

$28 ($48) OCR0B_7 OCR0B_6 OCR0B_5 OCR0B_4 OCR0B

Read/Write RW RW RW RW

Initial Value 0 0 0 0

Bit 3 2 1 0

$28 ($48) OCR0B_3 OCR0B_2 OCR0B_1 OCR0B_0 OCR0B

Read/Write RW RW RW RW

Initial Value 0 0 0 0

The Output Compare Register B contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC0B pin.

• Bit 7:0 – OCR0B_7:0 - Output Compare Register

17.9.7 TIMSK0 – Timer/Counter0 Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0

NA ($6E) Res4 Res3 Res2 Res1 Res0 OCIE0B OCIE0A TOIE0 TIMSK0

Read/Write R R R R R RW RW RW

Initial Value 0 0 0 0 0 0 0 0

• Bit 7:3 – Res4:0 - Reserved

This bit is reserved for future use. A read access always will return zero. A write access

does not modify the content.

• Bit 2 – OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match B interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0B bit is set

in the Timer/Counter0 Interrupt Flag Register TIFR0.

• Bit 1 – OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set

in the Timer/Counter0 Interrupt Flag Register TIFR0.

• Bit 0 – TOIE0 - Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed

if an overflow in Timer/Counter0 occurs i.e., when the TOV0 bit is set in the

Timer/Counter0 Interrupt Flag Register TIFR0.

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