Rainbow-electronics ATmega128RFA1 Uživatelský manuál stáhnout pdf (Strana 339)

339

8266A-MCU Wireless-12/09

ATmega128RFA1

23 USART

23.1 Features

• Full duplex operation (independent serial receive and transmit registers)

• Asynchronous or synchronous operation

• Master or slave clocked synchronous operation

• High resolution baud rate generator

• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

• Odd or even parity generation and parity check supported by hardware

• Data overrun detection

• Framing error detection

• Noise filtering includes false start bit detection and digital low pass filter

• 3 separate interrupts on TX complete, TX data register empty and RX complete

• Multi-processor communication mode

• Double speed, asynchronous communication mode

23.2 Overview

The Universal Synchronous and Asynchronous Serial Receiver and Transmitter

(USART) is a highly flexible serial communication device.

The ATmega128RFA1 has two USART’s, USART0 and USART1. The functionality for

all two USART’s is described below. USART0 and USART1 have different I/O registers

as shown in "Register Summary" on page 496.

A simplified block diagram of the USART transmitter is shown in Figure 23-1 on page

340 on page 340. CPU accessible I/O registers and I/O pins are shown in bold.

The Power Reduction USART0 bit, PRUSART0, in "PRR0 – Power Reduction

Register0" on page 167 must be disabled by writing a logical zero to it. The Power

Reduction USART1 bit, PRUSART1, in "PRR1 – Power Reduction Register 1" on page

168 must be disabled by writing a logical zero to it.

The dashed boxes in the block diagram Figure 23-1 on page 340 separate the three

main parts of the USART (listed from the top): clock generator, transmitter and receiver.

Control registers are shared by all units. The clock generation logic consists of

synchronization logic for external clock input used by synchronous slave operation, and

the baud rate generator. The XCKn (transfer clock) pin is only used by synchronous

transfer mode. The transmitter consists of a single write buffer, a serial shift register,

Parity generator and control logic for handling different serial frame formats. The write

buffer allows a continuous transfer of data without any delay between frames. The

receiver is the most complex part of the USART module due to its clock and data

recovery units. The recovery units are used for asynchronous data reception. In

addition to the recovery units, the receiver includes a parity checker, control logic, a

shift register and a two level receive buffer (UDRn). The receiver supports the same

frame formats as the transmitter, and can detect frame, data overrun and parity errors.

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Rainbow-electronics ATmega128RFA1 Uživatelský manuál Strana 339