Rainbow-electronics ATmega128L Uživatelský manuál stáhnout pdf (Strana 135)

135

ATmega128(L)

2467B–09/01

Extended Timer/Counter

Interrupt Mask Register –

ETIMSK

Note: This register is not available in ATmega103 compatibility mode.

• Bit 7:6 - Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices,

these bits must be set to zero when ETIMSK is written.

• Bit 5 - TICIE3: Timer/Counter 3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 3 input capture interrupt is enabled. The corresponding

interrupt vector (

See “Interrupts” on page 54.) is executed when the ICF3 flag, located in

ETIFR, is set.

• Bit 4 - OCIE3A: Timer/Counter 3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 3 output compare A match interrupt is enabled. The

corresponding interrupt vector (

See “Interrupts” on page 54.) is executed when the

OCF3A flag, located in ETIFR, is set.

• Bit 3 - OCIE3B: Timer/Counter 3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 3 output compare B match interrupt is enabled. The

corresponding interrupt vector (

See “Interrupts” on page 54.) is executed when the

OCF3B flag, located in ETIFR, is set.

• Bit 2 - TOIE3: Timer/Counter 3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 3 overflow interrupt is enabled. The corresponding

interrupt vector (

See “Interrupts” on page 54.) is executed when the TOV3 flag, located

in ETIFR, is set.

• Bit 1 - OCIE3C: Timer/Counter 3, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 3 output compare C match interrupt is enabled. The

corresponding interrupt vector (

See “Interrupts” on page 54.) is executed when the

OCF3C flag, located in ETIFR, is set.

• Bit 0 - OCIE1C: Timer/Counter 1, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the status register is set (interrupts glo-

bally enabled), the timer/counter 1 output compare C match interrupt is enabled. The

corresponding interrupt vector (

See “Interrupts” on page 54.) is executed when the

OCF1C flag, located in ETIFR, is set.

Bit 76543210

––TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C ETIMSK

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial value00000000

1 2 ... 130 131 132 133 134 135 136 137 138 139 140 ... 330 331

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