
81
ATmega128(L)
2467B–09/01
Register Description for
I/O Ports
Port A Data Register – PORTA
Port A Data Direction Register
– DDRA
Port A Input Pins Address –
PINA
Port B Data Register – PORTB
Port B Data Direction Register
– DDRB
Table 47. Overriding Signals for Alternate Functions in PG0
Signal Name PG0/WR
PUOE SRE
PUOV 0
DDOE SRE
DDOV 1
PVOE SRE
PVOV WR
DIEOE 0
DIEOV 0
DI -
AIO -
Bit 76543210
PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/WriteRRRRRRRR
Initial value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Komentáře k této Příručce