Rainbow-electronics ATmega128L Uživatelský manuál stáhnout pdf (Strana 258)

258

ATmega128(L)

2467B–09/01

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock

frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency

has to be at least five times the number of scan bits divided by the maximum hold time,

hold,max

ATmega128 Boundary-

scan Order

Table 107 shows the Scan order between TDI and TDO when the Boundary-scan chain

is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit

scanned out. The scan order follows the pin-out order as far as possible. Therefore, the

bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the

rules are the Scan chains for the analog circuits, which constitute the most significant

bits of the scan chain regardless of which physical pin they are connected to. In

Figure

123

, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn.

Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain,

since these pins constitute the TAP pins when the JTAG is enabled.

Verify the

COMP bit

scanned

out to be 0

1 0x200 0x08 1 1 0 0 0

7 1 0x200 0x08 0 1 0 0 0

8 1 0x200 0x08 1 1 0 0 0

9 1 0x143 0x08 1 1 0 0 0

10 1 0x143 0x08 1 0 0 0 0

Verify the

COMP bit

scanned

out to be 1

1 0x200 0x08 1 1 0 0 0

Table 106. Algorithm for Using the ADC

Step Actions ADCEN DAC MUXEN HOLD PRECH

PA3.

Data

PA3.

Control

PA3 .

Pullup_

Enable

Table 107. ATmega128 Boundary-scan Order

Bit Number Signal Name Module

204 AC_IDLE Comparator

203 ACO

202 ACME

201 AINBG

1 2 ... 253 254 255 256 257 258 259 260 261 262 263 ... 330 331

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