104
ATmega8515(L)
2512A–AVR–04/02
sequence. The synchronization prevents theoccurrenceof odd-length, non-symmetrical
PWM pulses, thereby making the output glitch-free.
The OCR1x Register access mayseem complex, but this is not case. When the double
buffering is enabled, the CPUhas access to the OCR1xBuffer Register, and ifdouble
buffering isdisabled the CPUwill access the OCR1xdirectly.The content of the OCR1x
(Buffer orCompare) Register is only changedbya write operation (theTimer/Counter
does not update thisregister automatically as theTCNT1 – andICR1 Register).There-
fore OCR1x is not read via the highbyte temporary register(TEMP). However, it is a
goodpracticetoread the lowbyte firstaswhen accessing other 16-bit registers. Writing
the OCR1x Registers must be done via theTEMP Registersincethe compareof all 16
bits isdone continuously.The highbyte (OCR1xH) has to be written first. When the high
byte I/Olocation iswritten by the CPU, theTEMPRegisterwill beupdatedbythevalue
written. Then when the lowbyte (OCR1xL) iswrittentothe lower eight bits, the highbyte
will be copied into theupper eight bits of either the OCR1xBuffer orOCR1xCompare
Register in the same system clock cycle.
For moreinformation ofhow to access the16-bit registers refer to “Accessing 16-bit
Registers”onpage 97.
Force Output Compare In non-PWM Waveform Generation modes, thematch output of the comparatorcan be
forcedbywriting a one to the
Force Output Compare
(FOC1x) bit. Forcing compare
match will not set the OCF1xflag orreload/clear thetimer, but the OC1xpin will be
updated as if a realcomparematch had occurred(the COM11:0 bitssettingsdefine
whether the OC1xpin isset,cleared or toggled).
Compare Match Blocking by
TCNT1 Write
All CPUwrites to theTCNT1 Registerwill block anycomparematch that occurs in the
nexttimerclock cycle, even when thetimer isstopped.Thisfeatureallows OCR1x to be
initialized to the same value as TCNT1 without triggeringaninterrupt when the
Timer/Counterclock is enabled.
Using the Output Compare
Unit
Since writing TCNT1 in any modeof operation will block all comparematchesfor one
timerclock cycle, thereare risks involvedwhen changing TCNT1 when using any of the
output compare channels, independent ofwhether theTimer/Counter isrunning or not.
If thevalue writtentoTCNT1 equals the OCR1x value, the comparematch will be
missed, resulting in incorrect waveform generation. Do not write theTCNT1 equal to
TOPinPWM modeswith variableTOPvalues.The comparematch for theTOP will be
ignored and the counterwill continue to 0xFFFF. Similarly, donotwrite theTCNT1 value
equal to BOTTOM when the counter isdowncounting.
The setup of the OC1xshould be performedbefore setting the Data Direction Register
for the port pin to output. Theeasiest way ofsetting the OC1x value is to usethe Force
Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Registerkeeps its
value even when changing between Waveform Generation modes.
Beawarethat the COM1x1:0 bits arenotdouble buffered togetherwith the compare
value. Changing the COM1x1:0 bitswill takeeffectimmediately.
(151 stránky)
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