83
ATmega8515(L)
2512A–AVR–04/02
the counter isrunning with none or a lowprescaler value must be done withcare since
the CTC mode does not have the double buffering feature. If thenew value written to
OCR0 islower than the current value of TCNT0, the counterwill miss the compare
match.The counterwill then have to count to its maximum value (0xFF) andwrap
aroundstarting at 0x00 beforethe comparematch can occur.
For generating a waveform output in CTC mode, the OC0 output can be set to toggleits
logicallevel on each comparematch by setting the Compare Output mode bits to toggle
mode (COM01:0 = 1).The OC0value will not bevisibleonthe port pin unless the data
direction for the pin isset to output. The waveformgeneratedwill haveamaximum fre-
quency off
OC0
=f
clk_I/O
/2 when OCR0 isset to zero (0x00).The waveform frequency is
definedbythe following equation:
The“
N
”variable represents the prescale factor(1, 8,64, 256, or 1024).
Asfor the Normal modeof operation, theTOV0 flag isset in the same timerclock cycle
that the countercountsfrom MAX to 0x00.
Fast PWM Mode The fastPulse WidthModulation orfastPWM mode (WGM01:0 = 1)provides a high
frequency PWM waveform generation option. The fastPWM differs from theother PWM
option by itssingle-slopeoperation. The countercountsfrom BOTTOM to MAX then
restartsfrom BOTTOM. Innon-inverting Compare Output mode, the Output Compare
(OC0) iscleared on the comparematch between TCNT0 andOCR0, andset at
BOTTOM. Ininverting Compare Output mode, the output isset on comparematch and
cleared at BOTTOM. Due to the single-slopeoperation, theoperating frequency of the
fastPWM mode can betwiceashigh as the phase correctPWM modethat use dual-
slopeoperation. Thishighfrequency makes the fastPWM mode well suitedforpower
regulation,rectification, andDAC applications. Highfrequency allows physically small
sized externalcomponents(coils, capacitors), and therefore reduces totalsystem cost.
In fastPWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timerclock cycle. The timing diagram
for the fastPWM modeisshowninFigure 38. TheTCNT0 value is in the timing diagram
shownas a histogram for illustrating the single-slopeoperation. The diagram includes
non-inverted and inverted PWM outputs.The small horizontalline marks on theTCNT0
slopesrepresent comparematchesbetween OCR0 and TCNT0.
f
OCn
f
clk_I/O
2 N 1 OCRn+()⋅⋅
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