
202
ATmega8515(L)
2512A–AVR–04/02
Figure 89. ExternalMemory Timing (SRWn1 = 0,SRWn0 = 0
Figure 90. ExternalMemory Timing (SRWn1 = 0,SRWn0 = 1)
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. Addr.
DA7:0
Address DataPrev. Data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. Addr.
DA7:0
Address
Data
Prev. Data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4
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