Rainbow-electronics ATmega8515L Uživatelský manuál Strana 153

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ATmega8515(L)
2512A–AVR–04/02
Buffer Registerdonotcontain data to betransmitted. When disabled, theTransmitter
will no longer overridetheTxD port.
Bit 2 – UCSZ2: Character Size
The UCSZ2 bitscombinedwith the UCSZ1:0 bit in UCSRCsets the number ofdata bits
(charactersize) in a frame the receiver and transmitter use.
Bit1–RXB8: Receive Data Bit 8
RXB8is theninthdata bit of the receivedcharacterwhen operating withserialframes
with nine data bits. Must be readbefore reading the lowbitsfrom UDR.
Bit0–TXB8:TransmitDataBit8
TXB8is theninthdata bit in the character to betransmittedwhen operating withserial
frameswith9data bits. Must be written before writing the lowbits to UDR.
USART Control and Status
Register C – UCSRC
The UCSRC Registershares the same I/Olocation as the UBRRH Register. See the
“Accessing UBRRH/UCSRC Registers”onpage 149which describeshow to access
thisregister.
Bit 7 – URSEL: Register Select
Thisbit selectsbetween accessing the UCSRC or the UBRRH Register. Itisread as
one when reading UCSRC.The URSEL must be one when writing the UCSRC.
Bit 6 – UMSEL: USART Mode Select
Thisbit selectsbetween asynchronous andsynchronous modeof operation.
Bit 5:4 – UPM1:0: Parity Mode
These bits enableandset typeofparity generation andcheck. If enabled, theTransmit-
terwill automatically generate andsend the parity of thetransmitteddata bitswithin
each frame. TheReceiverwill generate a parity value for theincoming data andcom-
pareittothe UPM0 setting. If amismatch isdetected, thePEflag in UCSRA will be set.
Bit 76543 210
URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value10000110
Table 63. UMSEL Bit Settings
UMSEL Mode
0AsynchronousOperation
1 SynchronousOperation
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